Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel, Johann; Sinanoglu, Ozgur; Elfadel, Ibrahim M.; Lienig, Jens; Sze, Cliff

doi:10.2197/ipsjtsldm.10.45

Cited by 42 publications

(23 citation statements)

References 137 publications

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“…3D integration has experienced significant traction over the recent years, for both improving scalability as well manufacturing and integration capabilities [6], [12], [13]. 3D integration can be broadly classified into four flavors ( Fig.…”

Section: D Integration and Cad Flowsmentioning

confidence: 99%

“…We assume that the attacker holds the layout files for the top and bottom tier, but, residing in the untrusted fab, she/he has no access to the trusted RDL. 6 Although she/he understands how many drivers are connecting from the bottom to the top tier and vice versa, she/he does not know which driver connects to which sink, given the randomization of F2F vias. Recall that, we do not engage in cross-tier optimization, to mitigate any layout-level hints.…”

Section: Our Proximity Attack For 3d Smmentioning

confidence: 99%

“…Independent of hardware security, 3D integration has made significant strides over recent years. The concept of 3D integration is to stack and interconnect multiple chips/dies/tiers/layers, thereby promising "More Moore," i.e., to overcome the scalability bottleneck which is exacerbated by ever-increasing challenges for pitch scaling, routing congestion, process variations, et cetera [6]. Recent studies and prototypes have shown that 3D integration can indeed offer significant benefits over conventional 2D chips [7], [8], which can ultimately also help to thoroughly utilize the existing technology nodes.…”

Section: Introductionmentioning

confidence: 99%

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

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Section: D Integration and Cad Flowsmentioning

confidence: 99%

Section: Our Proximity Attack For 3d Smmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

Self Cite

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“…Aside from the emerging devices outlined above, 3D and 2.5D integration targets at the system level. That is, these technologies embrace notions of "building skyscrapers" or "city clusters" of electronics [140][141][142][143]. Two factors drive these technologies: for one, that is the CMOS scalability bottleneck, which becomes more exacerbated for advanced nodes by issues like routability, pitch scaling, and process variations, for another, that is the need to advance heterogeneous and system-level integration.…”

Section: D and 25d Integrationmentioning

confidence: 99%

Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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“…A significant contributor to test time is the test vector transport phase in which a large volume of data is required to be serially shifted into the internal scan-chains [6]. 3D stacking brings about several additional and more complex challenges for test access [7][8] [9] [10]. First, higher transistor density increases the probability of manufacturing defects such as metal bridging, metal opens, via opens and transistor defects.…”

Section: Introductionmentioning

confidence: 99%

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

Soomro

Samie

Jennions

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to meet the increasing demand for more performance with reduced power consumption and chip formfactor, semiconductor manufacturing is moving towards 3D Stacked Integrated Circuits (SIC). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or Through Silicon Vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this paper, a test accessibility architecture based on ternary encoded Simultaneous Bi-Directional Signaling (SBS), intended for use in parallel Test Access Mechanism (TAM) in System on Chip (SoC) based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the Overall Test Time (OTT) by up to 53.6% as compared to conventional TAM design methods. Index Terms-3D Stacked Integrated Circuits, System on Chip, Design for Testability, Simultaneous Bi-directional, Test Access Mechanism© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2 the industry by the International Technology Roadmap for Semiconductors (ITRS) [11].In this paper, a novel Test Access Mechanism (TAM) design is proposed for 3D SICs that doubles the data transfer efficiency of the pins and TSVs, resulting in a substantial decrease of the test times. This is achieved by leveraging Simultaneous Bidirectional Signaling (SBS) for full-duplex test mode communication at chip terminals. SBS allows transmission and reception of test bits simultaneously compared to the conventional Uni-Directional Signaling (UDS) scheme in which the signal could travel in only one direction at a given time. Using SBS, a complete transmission and reception channel could be formulated using a single electrical path at the chip terminal instead of two, effectively doubling the number of test-channels and increased parallelism in test scheduling. The paper further discusses the TAM design considerations for the incorporation of SBS in 3D SICs such that it does not interfere with the functional mode performance and standard DFT logic, such as JTAG compliant boundary scan registers. An example implementation suitable for low-frequency test vector transportation is presented, and its electrical characteristics are discu...

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Cited by 42 publications

References 137 publications

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Hardware Security For and Beyond CMOS Technology

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

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