Low-Power Clock Tree Synthesis for 3D-ICs

Abstract

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees' dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV's large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates' insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV's placement. Compared with previous 3D clock tree synthesis techniques, our Kmeans clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

“…Our obtained results are compared with [1, 2] shown in Table 2. Our method gives better performance compared to [1, 2] as our segregation method efficiently segregates sinks and inserting the number of TSVs which are required for better wire length. We keep single TSVs in order to reduce wire length and also in some cases we insert multiple TSVs to choose the shortest path.…”

“…The diameter of the TSV, we use of simulation is 5 μm, and the minimum keep-out distance between centres of neighbouring TSVs is 12 μm [28]. Our obtained results are compared with [1,2] shown in Table 2. Our method gives better performance compared to [1,2] as our segregation method efficiently segregates sinks and inserting the number of TSVs which are required for better wire length.…”

“…This method is based on pair matching which is introduced to generate an initial tree topology with considering geometry, layer and activity information, and reduces power by 24.08% compared with conventional Nearest Neighbour Selection algorithm. The authors in [1] concentrated on a low-power clock 3D clock tree design problem. They used the clock gating method for the design, while satisfying the layout white-space constraint and zero clock skew.…”

“…After performing the segregation on each part, distance is being calculated and depending on the distance of the different dies, smallest length is being chosen by inserting TSVs. This is performed in O (1). The time complexity equivalent equation can be written as T(n) = S(4 k ) and n = 4 k Where S(n) is segregation function and k is number of level.…”

“…The electronics industries have enjoyed remarkable growth and innovations over the past decades [1, 2]. This growth has largely followed Moore's law.…”