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In 3D ICs, TSV cross coupling can seriously degrade circuit performance if it is not sufficiently considered in a design. Cross coupling is heavily dependent on how TSVs are placed, and should be considered during the floorplanning of the chip. In this work we propose a coupling-aware TSV placement algorithm that attempts to reduce both wirelength and TSV cross coupling. TSV shielding is another method for coupling mitigation, and the proposed algorithm combines coupling-aware TSV placement with shield insertion to yield better results than either technique alone. With regard to the most heavily coupled TSV pair in a design, our results show that applying both techniques simultaneously produces a 12.3% improvement in maximum S-parameter compared to traditional TSV placement which optimizes wirelength only. Using coupling-aware TSV placement or shield insertion alone produces a 4.2% and 4.8% improvement respectively. The improvement offered by using both techniques simultaneously is actually more than the sum of the improvement offered by using each technique on its own. This implies that the two techniques are not independent of one another, and that when used simultaneously each technique increases the effectiveness of the other, giving strong motivation for using them both simultaneously. Furthermore, the percent increase in wirelength due to using these two techniques is an order of magnitude less than the percent improvement to coupling, justifying the tradeoff made by our algorithm.