Continued frequency scaling in 3D ICs through micro-fluidic cooling

Serafy, Caleb; Srivastava, Ankur; Yeung, Donald

doi:10.1109/itherm.2014.6892267

Cited by 5 publications

(5 citation statements)

References 15 publications

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“…Several researches [4,26] demonstrate that leakage power can account for as much as 40% of the total power in FPGAs at sub-100nm technology nodes. Moreover, leakage power increases non-linearly with temperature [20] (as illustrated in Figure 1). The positive feedback between temperature and leakage power will lead to thermal runaway if 3D FP-GAs are not sufficiently cooled.…”

Section: Introductionmentioning

confidence: 92%

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Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Yang

Srivastava

2016

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Through Silicon Via (TSV) based 3D integration technology is a promising technology to increase the performance of FP-GAs by achieving shorter global wire-length and higher logic density. However, 3D FPGAs also suffer from severe thermal problems due to the increase in power density and thermal resistance. Moreover, past work has shown that leakage power can account for 40% of the total power at current technology nodes and leakage power increases non-linearly with temperature. This intensifies the thermal problem in 3D FPGAs and more aggressive cooling methods such as micro-channel based fluidic cooling are required to fully exploit their benefits. The interaction between micro-channel heat sink design and the performance of a 3D FPGA is very complicated and a comprehensive approach is required to identify the optimal design of 3D FPGAs subject to thermoelectrical constraints. In this work, we propose an analysis framework for 3D FPGAs embedded with micro-channelbased fluidic cooling to study the impact of channel density on cooling and performance. According to our simulation results, we provide guidelines for designing 3D FPGAs embedded with micro-channel cooling and identify the optimal design for each benchmark. Compared to naive 3D FPGA designs which use fixed thermal heat sink, the optimal design identified using our framework can improve the operating frequency and energy efficiency by up to 80.3% and 124.0%.

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Section: Introductionmentioning

confidence: 92%

“…The static power of a 3D-tile is γ × 10µW where γ is a scaling parameter equal to the ratio of the number of minimum width transistor areas (without considering the area occupied by TSVs) between a 3D-tile and a 2D-tile. Following this, we use the following equation [20] to extrapolate the static power for different temperatures:…”

Section: Static Powermentioning

confidence: 99%

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Yang

Srivastava

2016

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…So far, the 3D CPU with stacked-DRAM-on-logic structure has attracted wide interests due to its large bus bandwidth and the ability of parallel accessing to memory [16]. One structure of this kind of 3D CPUs is illustrated in Figure 4.…”

Section: Background and Test Vehiclementioning

confidence: 99%

“…In order to handle this trade-off, in this case study, we formulate the DRM problem as maximizing the 3D CPU performance subject to EM-induced 3D PDN reliability constraint. The text vehicle of this case study is adopted from [16] which is illustrated in Figure 4). Readers may refer to [16] for more details of this architecture.…”

Section: Background and Test Vehiclementioning

confidence: 99%

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Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors

Yang

Serafy

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

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In this paper, we propose a phase-driven Q-learning based dynamic reliability management (DRM) technique for multicore processors to solve DRM problems of maximizing the processor performance subject to a large class of reliability constraints by turning ON/OFF cores and dynamic voltage frequency scaling. Our technique utilizes the existing methods to detect program phases (i.e. [17]) and learns (rather than obtaining at the off-line stage) the optimal configuration of the multi-core processor for each phase. Our technique outperforms the existing learning-based DRM methods in managing programs with highly diverse phases. Our proposed technique is evaluated by solving a DRM problem in 3D CPUs of maximizing processor performance subject to the electromigration induced power delivery network reliability constraint. Compared to the latest Q-learning based DRM technique [11], our method can achieve more than 1.3x improvement in performance with 77% memory savings.

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