Online TSV health monitoring and built-in self-repair to overcome aging

Serafy, Caleb; Srivastava, Ankur

doi:10.1109/dft.2013.6653610

Cited by 20 publications

(5 citation statements)

References 13 publications

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“…For online testing, injected test patterns to the TSV can be captured at the output and analyzed to find open defects using a NAND gate with logic threshold voltage [12]. Serafy et al [13] presented a lifetime reliability using a resistance tracking method and BIST to overcome the aging in TSVs. In [17], the authors proposed a test access point for injecting and collecting test vectors while Van der Plas et al [6] used a test pattern generator to test open TSV defects.…”

Section: Related Workmentioning

confidence: 99%

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A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

et al. 2020

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Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R + 1 defects. Moreover, by using G groups, it can localize up to G × R and detect up to G × (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

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Section: Related Workmentioning

confidence: 99%

“…To localize the defective position, most systems use Builtin-self-test (BIST) [9], external testing [10], [11] and online testing [12], [13]. The mentioned works mostly focused on issuing test patterns and capturing them on a different terminal of a TSV to identify their healthiness.…”

Section: Introductionmentioning

confidence: 99%

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

et al. 2020

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“…It is unique in the following aspects. First, unlike previous intrusive methods [4] [5], it can operate independently without system support and will not interfere with system operation. Second, it can monitor the performance of targeted interconnects directly and continuously.…”

Section: Case Studiesmentioning

confidence: 99%

“…An intrusive method needs to halt the system operation periodically to perform the Built-In Self-Test (BIST) to decide if there is any sign of timing failure [4] [5]. To support this type of method, numerous delay test methods can be applied [6] [7][8] [9].…”

Section: Introductionmentioning

confidence: 99%

“…(1) As compared to previous intrusive method [4][5] for interconnects (e.g., by periodic BIST and repair), the proposed method does not require the system-level support and therefore is much easier to implement. Also, it is able to catch those timing failure threats that occur only when the system is operating under some worst-case scenarios which may not be observable in an off-line built-in self-test session.…”

Section: Introductionmentioning

confidence: 99%

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On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs

Huang

Zeng

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro-migration effects that could lead to unexpected resistance increase after certain time of field operation. To cope with this reliability threat, we present an on-line monitoring method that aims to continuously detect excessive transition time occurring to a TSV (which often indicates performance degradation). Our method attaches a monitor to the termination end of a TSV. Any transition there is converted into a pulse-width, which is further compared to a dynamically tunable threshold. A Timing Failure Threat (TFT) is thereby detected when the pulse-width exceeds the threshold. This method can be applied to a large number of TSVs easily since the monitoring results are binary and can be stored in FFs forming a scan chain for easy access.

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Overview of On-Chip Performance Monitors for Clock Signals

Huang

2020

2020 IEEE 29th Asian Test Symposium (ATS)

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Online TSV health monitoring and built-in self-repair to overcome aging

Cited by 20 publications

References 13 publications

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs

Overview of On-Chip Performance Monitors for Clock Signals

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