TSV-Based 3-D ICs: Design Methods and Tools

Lu, Tiantao; Serafy, Caleb; Yang, Zhiyuan; Samal, Sandeep Kumar; Lim, Sung Kyu; Srivastava, Ankur

doi:10.1109/tcad.2017.2666604

Cited by 44 publications

(17 citation statements)

References 180 publications

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“…ment [3], [13], [33], [34], [35], [36]. Note that TSVs do not scale at the same rate as transistors, thus the mismatch between TSV and cell dimensions will remain for future nodes and may even increase [37].…”

Section: Tsv-based 3d Icsmentioning

confidence: 99%

“…Successful adoption of 3D chips requires addressing different classical and novel challenges which simultaneously affect the manufacturing processes, design practices and physical design tools [3], [9], [10], [11], [12], [13]. If not properly addressed, these fairly complex challenges (such as adverse coupling effects [14], [15]) may render 3D chips commercially unviable.…”

Section: Introductionmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Tsv-based 3d Icsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…With the rapid development of electronic science and technology, 3-D integrated circuit (3-D IC) technology emerging as a powerful tool for satisfying requirements for the challenging integrated circuit packaging has received tremendous attention in the semiconductor community [1][2][3][4]. By expanding the design space into the third dimension, 3-D IC obtains significant electrical performance benefits compared with previous packaging technologies, such as better performance, reduced average wire length, wire delay, lower power consumption and footprint, etc.…”

Section: Introductionmentioning

confidence: 99%

Thermal management of the through silicon vias in 3-D integrated circuits

2019

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The through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit integration. However, its size and the property of the filled-materials are two factors affecting the thermal behavior of the integrated circuits. In this paper, we design 3-D integrated circuits with different through silicon via models and analyze the effect of different material-filled through silicon vias, aspect ratio and thermal conductivity of the dielectric on the steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for through silicon vias in 3-D integrated circuits.

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“…Moreover, 3D-ICs also offer the potential for heterogeneous integration, which is essential for More than Moore (MtM) technology [3]. 3D integration has already seen commercial applications in the form of 3D memory but there are still significant open problems in both research and implementation [4]. In this work, we will focus on the TSV reliability problem.…”

Section: Introductionmentioning

confidence: 99%

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Chen

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming (ILP) based model to construct adaptive fault-tolerance structure with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through efficient min-cost-max-flow (MCMF) model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive faulttolerance structures. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.Index Terms-3D-IC, fault-tolerance, TSV planning, TSV yield.

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TSV-Based 3-D ICs: Design Methods and Tools

Cited by 44 publications

References 180 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Thermal management of the through silicon vias in 3-D integrated circuits

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

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