Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Abstract

In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming (ILP) based model to construct adaptive fault-tolerance structure with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through efficient min-cost-max-flow (MCMF) model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive faulttolerance structures. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.Index Terms-3D-IC, fault-tolerance, TSV planning, TSV yield.

Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits

“…A recent work [22] has introduced an adaptive faulttolerance structure generation method. In this method, a TSV repair structure is adaptively generated.…”

“…It considers varying the fault-tolerance of TSV repair groups and assigning spares from a large number of candidates while minimizing the hardware-cost and efficiently utilizing the spare TSVs. The proposed vritualiztion-based TSV repair concept is applicable to the adaptive fault-tolerance structure generation methods such as [22] for more efficient utilization of the spare TSVs. As such, the proposed method enhances the fault-tolerance capability of an individual spare TSV and is, therefore, orthogonal to the conventional techniques which focus on effective spare TSVs placement topologies.…”