An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach

Nair, Radeep Krishna Radhakrishnan; Sivakumar, P.; Nair, T. R. Radhakrishnan; Cengiz, Korhan

doi:10.1007/s12652-021-02964-w

Cited by 5 publications

(3 citation statements)

References 41 publications

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“…First, the TSV defect equivalent circuit is obtained, and the multi-tone signal with Gaussian white noise is added as the excitation of the test simulation to extract the peak-to-average ratio for fault detection; the accuracy of this method can reach the micrometer level. Nair et al [37] used Adam's deep neural network algorithm to detect faulty TSVs in 3D-IC. Compared with the traditional random gradient algorithm, it has fast performance and a better convergence speed.…”

Section: Metal Fillmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

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Section: Metal Fillmentioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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“…The schematic diagram of the TSV 3D packaging structure is shown in Figure 1. 1–4 Since TSV gradually develops toward smaller sizes, the scale effect is more obvious and the stress mismatch is more serious, resulting in defects such as bottom voids, gaps and filling missing. 5–7 The existence of these defects can adversely affect the performance of electronic devices, reduce the reliability of the device, and even damage the device.…”

Section: Introductionmentioning

confidence: 99%

Internal defect identification method of TSV 3D packaging based on built-in integrated sensor

Huang

Yin

Liu

et al. 2022

Advances in Mechanical Engineering

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TSV (Through Silicon Via) is a key technology for three-dimensional (3D) packaging due to its unique vertical interconnection method. However, its particular manufacturing process of-ten leads to internal defects, such as gaps, bottom voids, filling missing, which are usually difficult to be detected by common means. In order to discover the internal defect of TSV packaging effectively, a novel non-destructive inspection method based on built-in integrated temperature sensor array is proposed. The relationship between temperature distribution and internal defect is dis-covered and then corresponding sensor array layout is designed. The simulation analysis shows that this kind of sensor array can recognize the internal TSV defect. And supervised machine learning is used to construct the classification model by which different defects can be found and classified with relatively high accuracy, and the classification accuracy rate can reach 95.625%. Experiments were conducted and the rationality of this built-in sensing array was verified. The research provides a non-destructive testing method for TSV internal defects based on bulit-in-integrated sensors, and verifies the feasibility of sensor arrangement through simulation, laying a foundation for the realization of later TSV design optimization.

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“…During the IC fabrication, there may be a chance for TSV to become defective and it must be identified to increase the performance of the system. To resolve this problem, many faulty TSV detection techniques are introduced [15], [16], [17], [18], [19].…”

Section: Introductionmentioning

confidence: 99%

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC

Kaibartta¹,

Biswas²,

Pal³

et al. 2021

IEEE Access

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Demand for small, multi functional, high performance electronic product with less power consumption is increasing rapidly. To meet the demand, IC design has been shifted from two dimensional integrated circuit (2D-IC) to three dimensional integrated circuit (3D-IC), where multiple device layers are stacked together to create stacked integrated circuit (SIC). This results the complexity in 3D SIC architecture and increase in the number of fault-sites. Therefore, testing of SIC has become complicated. Consequently, the test data volume also grows in proportion to the number of cores in the SIC, since each core is associated with one or more tests, which leads to longer test times. Test cost of IC which depends on test time, associated hardware to test the cores and the power dissipated at the time of test, can be represented as a weighted sum of test time and the associated hardware to test the core with power considered as the test constraint. As a result an efficient test plan is required to co-optimize test time and hardware under certain power constraint. The objective of our work is to design an efficient test plan both for non stacked IC ( i.e. SIC with single chip) and 3D stacked IC (i.e. SIC with multiple chips) under a power constraint, where each chip is provided with IEEE 1149.1 architecture. An existing cost model is used for calculating the test cost. Initially we propose First fit based two dimensional (2D) Bin Packing optimization algorithm for minimizing the test cost of non stacked IC. However, the method produces sub-optimal result in comparison to earlier reported work. Knowing the complexity of 3D SIC, Genetic algorithm based metaheuristic approach is next proposed in this paper. It is applied on several ITC02 benchmark circuits and the experimental result shows the efficacy of the proposed algorithm in comparison to earlier works.

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An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach

Cited by 5 publications

References 41 publications

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Internal defect identification method of TSV 3D packaging based on built-in integrated sensor

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC

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