Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling

Design Space Modeling and Simulation for Physically Constrained 3D CPUs

“…Cache and register latencies are determined using CACTI [21] to provide realistic architectural setups to the simulator. DRAM latency is calculated using the model proposed in [18] and NOC topology/latency is calculated as explained in Section 2.4. M2S simulates the execution of an x86 binary file on the described CPU.…”

“…• Layer aspect ratio ( i • widthcore /j•heightcore) is relatively square. NOC topology is defined as an i × j × k 3D mesh [18] and NOC latency is defined as the wire delay of length max(width core , height core ), calculated using the wire delay model from [16] with technology parameters extracted from McPAT source code. NOC topology and latency are fed back into the performance simulator to get accurate inter-core communication simulations.…”

“…We consider 3D CPUs with stacked DRAM which is considered to be one of the primary advantages of 3D CPUs [10,14]. By integrating the DRAM on chip using through silicon vias (TSVs), the core-memory bandwidth can be increased drastically due to increased memory bus width, more memory controllers and faster bus speed [15,18].…”

“…Vertical integration of circuits (3D ICs) is an up-and-coming technology that shows great potential towards improving circuit power and performance as well as facilitating new CPU architecture paradigms such as stacked memory and highly connected onchip networks [18]. However 3D ICs also bring new challenges, chief among them thermal management [15,19], and moves the architectural design problem into uncharted territory where traditional domain knowledge and designer intuition may no longer apply.…”

“…However 3D ICs also bring new challenges, chief among them thermal management [15,19], and moves the architectural design problem into uncharted territory where traditional domain knowledge and designer intuition may no longer apply. Moreover, past work [18,19] has shown that significant portions of the 3D CPU design space can be infeasible due to physical con-Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.…”