Reliability issues related to Fast Charge Loss Mechanism in Embedded Non Volatile Memories

Mora, P.; Renard, S.; Bossu, G.; Waltz, P.; Pananakakis, G.; Ghibaudo, G.

doi:10.1109/irws.2006.305213

Cited by 6 publications

(8 citation statements)

References 11 publications

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“…Temperature effects of kinetic response.-Furthermore, the mechanism is temperature activated, in agreement with fast charge loss in memory data retention studies. 3 As illustrated by Fig. 12, faster kinetics are reached at an elevated temperature.…”

Section: Influent Parameters On Kinetic Responsementioning

confidence: 88%

“…Considering that the same mechanism is achieved for each a-Si x N y :H recipe, hysteresis opening differences and associated charge quantity could explain the behavior differences observed on active devices. 3,4 However, the non-steady state induced by the hysteresis made the interpretation and comparison of each recipe more difficult.…”

Section: Analysis Of Non-steady-state C-v Characteristicsmentioning

confidence: 99%

“…However, it is now well known for influencing active device performances: its mechanical stress enables it to improve metal oxide semiconductor ͑MOS͒ transistor performances, 2 but its composition can also be at the origin of reliability issues like charging damage, 3 data retention degradation for single polysilicon flash memory, and high-voltage MOS aging acceleration. 4 In recent studies, it has been reported that a-Si x N y :H composition modifies the dynamic of charge loss in nonvolatile memory, 3 and this wear out has been ascribed to mobile charge in the a-Si x N y :H. 5 In this context, a new methodology is presented in order to determine the trapped charge kinetics in such a film. It is based on capacitance vs time ͑C-t͒ measurements performed on metal insulator semiconductor ͑MIS͒ structures after an initial setup of charge achieved by capacitance vs voltage ͑C-V͒ hysteresis.…”

mentioning

confidence: 99%

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New Characterization Methodology of Borderless Silicon Nitride Charge Kinetics Using C-V Hysteresis Loops

Beylier¹,

Bruyère²,

Mora³

et al. 2008

J. Electrochem. Soc.

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In this paper, a new characterization methodology of borderless silicon nitride is presented. This material, deposited by a plasmaenhanced chemical vapor deposition process, contains a large charge quantity attributed to K centers. A steady-state capacitancevoltage ͑C-V͒ behavior has been researched, while taking into account charge considerations, electrical field, and time influence. It is achieved by a capacitance vs time at constant voltage experiment after a complete C-V hysteresis used to set up an initial state of charge. The charge evolution occurring during stress time is related to the charge-transformation kinetics. An empirical kinetic model has been extracted from these results, with time constant dependent on field and temperature. A faster positive to negative charge transformation has been shown, attributed to an easier hole trapping. Finally, this new characterization method demonstrates that data retention charge loss is correlated with trapping kinetics in borderless silicon nitride.

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Section: Influent Parameters On Kinetic Responsementioning

confidence: 88%

Section: Analysis Of Non-steady-state C-v Characteristicsmentioning

confidence: 99%

mentioning

confidence: 99%

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New Characterization Methodology of Borderless Silicon Nitride Charge Kinetics Using C-V Hysteresis Loops

Beylier¹,

Bruyère²,

Mora³

et al. 2008

J. Electrochem. Soc.

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“…One of the key reliability concerns for MTP application is DR window closure. Rather than the conventional tunnel oxide leakage model for eFlash, DR degradation model of logic eNVM is attributed to capacitive effect [1][2][3] in which the intrinsic DR behaviors are well established.…”

Section: Introductionmentioning

confidence: 99%

Investigation of data retention window closure on logic embedded non-volatile memory

Liao

Tsai

Leu

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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Two mechanisms of data retention (DR) are investigated on logic embedded non-volatile memory (eNVM) in Multiple-Time-Programming (MTP) application. Unlike the typically observed DR degradation after endurance test in flash memory, DR window closure of logic eNVM can be recovered at higher data retention bake temperature and longer bake time due to thermally activated electron de-trapping from interface of tunnel oxide to Si substrate. In addition, a new DR degradation mechanism called Reverse Code Effect (RCE) is shown to exhibit faster DR degradation than the original DR behaviors. RCE induced DR degradation can be attributed to the combined effect of capacitive coupling [1] in between floating gate (FG) and contact-etch-stop-layer (CESL) dipole charges and charge loss due to charge recombination in FG.We also demonstrate that RCE can be effectively suppressed by adopting low-level Si-H compositions of CESL nitride film with less dipole charges to reduce the charge loss in the FG.

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“…However, it is now well known for influencing active device performances: its mechanical stress enables to improve MOS transistor performances (2), but its composition can also be at the origin of reliability issues like charging damage (3), data retention degradation for single polysilicon flash memory and high voltage MOS aging acceleration (4). In recent studies, it has been reported that a-Si x N y :H composition modifies the dynamic of charge loss in non volatile memory (3) and this wearout has been ascribed to mobile charge in the a-Si x N y :H (5). In this context, a new methodology will be presented in order to determine the trapped charge kinetics in such a film.…”

Section: Introductionmentioning

confidence: 99%

New Characterization Methodology of Borderless Silicon Nitride Charge Kinetic using C(V) Hysteresis Loops

et al. 2007

View full text Add to dashboard Cite

In this paper a new characterization methodology of borderless silicon nitride is presented. This material, deposited by Plasma Enhanced Chemical Vapor Deposition process, contains a large charge quantity attributed to K centres. Actually, a steady state has been searched, while taking into account charge considerations, electrical field and time influence during C(V) hysteresis. It is achieved by a capacitance versus time at constant voltage experiment, after a complete C(V) hysteresis used to set up an initial state of charge. The charge evolution occurring during stress time is related to the charge transformation kinetics. An empirical kinetic model has been extracted from these results, with time constant dependent on field and temperature. A faster positive to negative charge transformation has been shown, attributed to an easier holes trapping. Finally, this new characterization method demonstrates that data retention charge loss is correlated to trapping kinetics in borderless silicon nitride.

show abstract

Reliability issues related to Fast Charge Loss Mechanism in Embedded Non Volatile Memories

Cited by 6 publications

References 11 publications

New Characterization Methodology of Borderless Silicon Nitride Charge Kinetics Using C-V Hysteresis Loops

New Characterization Methodology of Borderless Silicon Nitride Charge Kinetics Using C-V Hysteresis Loops

Investigation of data retention window closure on logic embedded non-volatile memory

New Characterization Methodology of Borderless Silicon Nitride Charge Kinetic using C(V) Hysteresis Loops

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