Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI

Urban, Christoph; Emam, Mostafa; Sandow, C.; Knoch, J.; Zhao, Qing‐Tai; Raskin, Jean‐Pierre; Mantl, S.

doi:10.1109/led.2010.2045220

Cited by 23 publications

(13 citation statements)

References 18 publications

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“…Today, new channel materials are considered such as Ge and III–V for holes and electrons transport, respectively. Raised source and drain regions and silicidation as well as low Schottky barrier source and drain contacts have been proposed those last years to minimize their impact on the static and dynamic transistor behaviors. Modification of the device architecture such as introduction of faceted source and drain , low‐k spacer materials , gate capping layer thickness, and gate height have been used recently to reduce the fringing parasitic capacitance effect.…”

Section: Discussionmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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SUMMARYSeveral physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band.

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Section: Discussionmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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“…This is especially true in Schotttky barrier MOS-FET applications. [70,71] F implantation into silicide [72] or before silicide [73] is known to improve NiSi thermal stability and increase dopant pile up.…”

Section: Increasing Interface Doping Concentrationmentioning

confidence: 99%

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Song

Blatchford

2011

Electron. Mater. Lett.

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TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

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“…A thermal annealing step is then carried out to drive the dopants into Si. This method is an alternative to silicidation induced dopant segregation [3] and may become more important for scaling applications. Firstly, the silicon substrate is not damaged prior silicidation.…”

Section: Barrier Lowering By Implantation Into Silicide (Iis)mentioning

confidence: 99%

“…It is known that a damaged silicon shows larger line edge roughness in the resulting S/D silicide. Secondly, the dopants segregate at the silicide/silicon interface if their solubility in the silicide is lower than in silicon [3][4][5], reducing the effective SBH. In general it is helpful for IIS processes, if the silicide has a high thermal stability to ensure that the dopants can be activated at higher temperatures.…”

Section: Barrier Lowering By Implantation Into Silicide (Iis)mentioning

confidence: 99%

“…However, SB-MOSFETs with large SB heights suffer from low on currents, a poor subthreshold swing and an ambipolar switching behavior due to high Schottky barriers. Processes based on silicidation induced dopant segregation [3][4][5][6][7] and barrier lowering by dopant implantation into the silicide (IIS) [5,7] reduce the effective Schottky barrier height (SBH), without diffusion of the dopants far into the channel. In this work, we investigate electrical properties of SBMOSFETs with gate length down to 20nm.…”

Section: Introductionmentioning

confidence: 99%

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20nm Gate length Schottky MOSFETs with ultra thin NiSi/epitaxial NiSi<inf>2</inf> source/drain

Knöll

Zhao

Lupták

et al. 2011

Ulis 2011 Ultimate Integration on Silicon

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Schottky barrier (SB)-MOSFETs with NiSi and epitaxial NiSi 2 S/D contacts with gate lengths as small as 20nm are presented. Epitaxial NiSi 2 FETs show higher on-currents than corresponding NiSi devices due to its lower SB height. A striking observation is that tunnelling currents through the fairly large SB decrease at very short gate lengths in SB-MOSFETs, in contrast to the scaling behavior of conventional MOSFETs. Simulations indicate that the potential in the channel increases due to overlap of the high source and drain barriers with decreasing gate length, leading to lower currents. Boron implantation into the silicide (IIS) was used to lower the SBH. Devices with epitaxial NiSi 2 show an improved performance after barrier lowering by dopant implantation into the silicide (IIS).

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Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on Thin-Body SOI

Cited by 23 publications

References 18 publications

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

20nm Gate length Schottky MOSFETs with ultra thin NiSi/epitaxial NiSi<inf>2</inf> source/drain

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