Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Abstract

TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

“…Literatures show that 45/32/22-nm-node Si CMOS technologies commonly use the gate-last high-/metal gate structure and the in-situ doped embedded SiGe for the source/drain regions of p-channel devices. [11][12][13][14] Therefore, these two components are used as a basis of the new device. Figure 1 summarizes the concept of the proposed device.…”

Wet Etch Rate Behavior of Poly-Si in TMAH Solution at Various Ambient Gas Conditions

“…As the demand for greater speed in semiconductor devices continues, a typical method of increasing charge mobility is to maximise the silicon strain at the depletion region in p-type transistors through the implementation of "Sigma Cavity" structures in the bulk silicon on either side of the gate structure. These structures, when filled, exhibit a uniaxial strain in the depletion region thus, increasing the charge transport speed [1]. The shape of the Sigma Cavity structure is important in maximising the strain in this region, thus strict control of the shape dimensions is imperative to the electrical performance of the device.…”

Effects of piezoresistivity of pentacene channel in organic thin film transistors under mechanical bending

“…[26][27][28] However, research on organic semiconductors has shown little progress compared to that on inorganic semiconductors. In the case of pentacene, there have been reports on the influence of static mechanical bending on device performance.…”