One chip solution for SMPS (Switch Mode Power Supply) has been drawing great attention of the designers with its green mode standby power and high efficiency in the AC-DC adaptor and LED lighting applications. The UHV (ultra-High Voltage) foundry process, which enables the integration solution for green compliance SMPS, is proposed in this paper. The technology integrated low voltage CMOS (5V), medium voltage (40V) and UHV (700V) devices in one single process. The UHV technology provides a novel UHV device structure with RESURF (Reduce-SURface-Field) effect to sustain ultra-high breakdown voltage and not to affect the original low/medium voltage devices performance in the same time. Thus, the concept of this novel structure is easily to apply to the other technology nodes and extend its voltage-sustaining range by adjusting the drift length for the RESURF structure. In this research, The 700V technology has realized the performance that the BVdss (breakdown voltage) is 800V with Ron sp (on-resistance) of 27OmOhm-cm2. In the same time, the process challenge to optimize 700V device performance against un-balanced mobile charge issue was also discussed.
Describe the purpose With the continuous development of domestic high-tech semiconductor technology, the process components and line width have gradually entered the 32-nanometer generation. For this high-end process technology, the airborne molecular contaminant has been the one of the key factors that affects the process yield. The airborne molecular contaminants would induce chemical reaction (acid-base reactions, redox reactions) and the product components would be adsorbed or deposited on the wafer surface and result in wafer defects or process component of the lower reliability. Therefore semiconductor AMC issues have reached attentions, particularly by the high-end wafer fab.
As the demand for greater speed in semiconductor devices continues, a typical method of increasing charge mobility is to maximise the silicon strain at the depletion region in p-type transistors through the implementation of “Sigma Cavity” structures in the bulk silicon on either side of the gate structure. These structures, when filled, exhibit a uniaxial strain in the depletion region thus, increasing the charge transport speed [1]. The shape of the Sigma Cavity structure is important in maximising the strain in this region, thus strict control of the shape dimensions is imperative to the electrical performance of the device.
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