One chip solution for SMPS (Switch Mode Power Supply) has been drawing great attention of the designers with its green mode standby power and high efficiency in the AC-DC adaptor and LED lighting applications. The UHV (ultra-High Voltage) foundry process, which enables the integration solution for green compliance SMPS, is proposed in this paper. The technology integrated low voltage CMOS (5V), medium voltage (40V) and UHV (700V) devices in one single process. The UHV technology provides a novel UHV device structure with RESURF (Reduce-SURface-Field) effect to sustain ultra-high breakdown voltage and not to affect the original low/medium voltage devices performance in the same time. Thus, the concept of this novel structure is easily to apply to the other technology nodes and extend its voltage-sustaining range by adjusting the drift length for the RESURF structure. In this research, The 700V technology has realized the performance that the BVdss (breakdown voltage) is 800V with Ron sp (on-resistance) of 27OmOhm-cm2. In the same time, the process challenge to optimize 700V device performance against un-balanced mobile charge issue was also discussed.
Selective area epitaxial (SAE) growth of strained SiGe:B (Boron) in the recessed source/drain (S/D) region of an MOS device is known to improve Si-PMOS performance due to enhancement of hole mobility and reduction of S/D resistance. However, the process may be adversely affected by pattern loading effects, SiGe relaxation, dislocation formation, dopant precipitation and contamination. These effects, if not controlled, will deteriorate device performance and yield. A nondestructive, in-line SAE process monitoring approach on patterned wafers is especially desired. A specialized, contact-less, carrier lifetime-based Room Temperature -Photoluminescence (RT-PL) method meets this demand. The RT-PL tool, which uses a novel excitation path design to achieve carrier confinement, device-suitable probing depth, submicron scanning resolution and a micron probe size, offers a quick, non-destructive assessment of strain, defects and contamination for SAE. In this paper, a systematic evaluation of blanket and selective growth layers is illustrated using layers with a Ge content of 15-25%, undoped and B-doped at ~10 20 cm -3 concentration. For the as-grown conditions, we observed that SiGe remains in an unrelaxed state without extended dislocations being formed. These results suggest that SiGe composition could be further modified to optimize the associated mobility enhancement. Uniformity variations associated with SiGe composition and B-doping were identified. Excessive boron precipitation, metallic particle-originated defects and large contamination regions induced by processing tools were also exposed. The multiple and unique insights enabled through the RT-PL technique provide significant benefits towards decreasing process development and integration time, maintaining SiGe process in control and reducing device fabrication costs.
Describe the purpose With the continuous development of domestic high-tech semiconductor technology, the process components and line width have gradually entered the 32-nanometer generation. For this high-end process technology, the airborne molecular contaminant has been the one of the key factors that affects the process yield. The airborne molecular contaminants would induce chemical reaction (acid-base reactions, redox reactions) and the product components would be adsorbed or deposited on the wafer surface and result in wafer defects or process component of the lower reliability. Therefore semiconductor AMC issues have reached attentions, particularly by the high-end wafer fab.
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