Origin of flat band voltage shift in HfO2 gate dielectric with La2O3 insertion

Kakushima, Kuniyuki; Okamoto, Koji; Adachi, Manabu; Tachi, Kazuyuki; Ahmet, Parhat; Tsutsui, Kazuo; Sugii, Nobuyuki; Hattori, Takeo; Iwai, Hiroshi

doi:10.1016/j.sse.2008.04.015

Cited by 56 publications

(51 citation statements)

References 7 publications

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“…Fig. 66 illustrates the bonding configurations for SiO 2 /Si, La 2 O 3 /Si, HfO 2 /Si, La 2 O 3 /IL/Si and HfO 2 /IL/Si interfaces [364]. Since the valences of La and Hf are 3 and 4, respectively, overall dipole moments at (b) La 2 O 3 /Si interface and (c) HfO 2 /Si interface will be 2/3l LaÀO À 1/2l SiÀO and 1/2l HfÀO À 1/2l SiÀO .…”

Section: Work Function Tuning By Interfacial Dipole In High-k Gate Stmentioning

confidence: 99%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

133

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Section: Work Function Tuning By Interfacial Dipole In High-k Gate Stmentioning

confidence: 99%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

133

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“…It implies that the V fb shift with La incorporation is not induced by the fixed charges. The interface dipole model has been proposed to explain the V fb shift [25]. In fact, there are several reasons for the dipole formation including the group electronegativity, oxygen vacancies, and oxygen ion density.…”

Section: Fb Modulation With Rare Earth Doping In Nmosmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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“…It has been reported that both Al and rare earth metals show significant diffusion in Hf-based gate stacks. 1,5,9 Upon diffusion, the aluminum and rare earth metals were found to react with the gate dielectric and interfacial SiO 2 layers. Some studies suggested the formation of silicates such as LaSiO x at the interface near the substrate, 14 while others indicated the formation of a HfLaSiO gate dielectric as a result of these reactions.…”

Section: à3mentioning

confidence: 99%

“…In addition, several models have already been proposed to explain the capping layer effect on flatband voltage (V FB ). [8][9][10][11][12] However, one area that has not been systematically investigated is the effect of the composition of the dielectric below the capping layer on the magnitude of the flatband voltage shift. In this article, we have investigated four different types of capping layers deposited on dielectrics with varying compositions.…”

mentioning

confidence: 99%

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

Caraveo-Frescas

Wang

Schwingenschlögl

et al. 2012

Applied Physics Letters

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The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

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Origin of flat band voltage shift in HfO2 gate dielectric with La2O3 insertion

Cited by 56 publications

References 7 publications

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Interface dipole engineering in metal gate/high-k stacks

Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

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