The development of transparent p-type oxide semiconductors with good performance could be a true enabler for a variety of applications, where transparency, power efficiency and more circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, we review recent developments in materials and devices based on p-type oxide semiconductors, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides and nickel oxides. The crystal and electronic structures of these materials are reviewed, along with approaches to enhance valence band dispersion to reduce effective mass and increase mobility.Strategies to reduce the interfacial defects, off state current, and material instability are discussed. Furthermore, we show that promising progress has been made in the performance of various type of devices based on p-type oxides. For example, transparent oxide-based p-n junction diodes have experienced significantly improved performance, where rectification ratios >10 7 have been achieved. The performances of thin-film transistors and inverters have also been modestly improved. For example, thin-film transistors with field-effect mobilities exceeding 5 cm 2 V -1 s -1 have been reported. In addition, several innovative approaches were developed to fabricate transparent complementary metal oxide semiconductor (CMOS) 2 devices. These approaches include novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains (as high as 120 has been demonstrated).Some progress has also been made in reducing the interfacial defects and off state currents using capping layers, high quality dielectrics and surface treatments. Resistive memory devices and hole transport layer in optoelectronic devices, mostly based on nickel oxide, have made decent progress. Transparent ferroelectric memory devices comprising p-type oxides have also been reported recently showing good hole mobilities (~3.3 cm 2 V -1 s -1 ) and good retention characteristics. This even includes multistate memory devices that show good stability. Nanoscale (e.g. nanowire) devices have now been reported using p-type oxides and do show performance improvements at scaled device geometry. New process developments have been reported, and some p-type oxides can now be deposited using atomic layer deposition and chemical routes, with promising performances. However, despite these recent developments, p-type oxides still lag in performance behind the n-type counterparts, which have entered volume production in the display market. The recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented in this review.

Here, we report the fabrication of nanoscale (15 nm) fully transparent p-type SnO thin film transistors (TFT) at temperatures as low as 180 °C with record device performance. Specifically, by carefully controlling the process conditions, we have developed SnO thin films with a Hall mobility of 18.71 cm(2) V(-1) s(-1) and fabricated TFT devices with a linear field-effect mobility of 6.75 cm(2) V(-1) s(-1) and 5.87 cm(2) V(-1) s(-1) on transparent rigid and translucent flexible substrates, respectively. These values of mobility are the highest reported to date for any p-type oxide processed at this low temperature. We further demonstrate that this high mobility is realized by careful phase engineering. Specifically, we show that phase-pure SnO is not necessarily the highest mobility phase; instead, well-controlled amounts of residual metallic tin are shown to substantially increase the hole mobility. A detailed phase stability map for physical vapor deposition of nanoscale SnO is constructed for the first time for this p-type oxide.

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

Transparent p-type materials with good mobility are needed to build completely transparent p-n junctions. Tin monoxide (SnO) is a promising candidate. A recent study indicates great enhancement of the hole mobility of SnO grown in Sn-rich environment [E. Fortunato et al., Appl. Phys. Lett. 97, 052105 (2010)]. Because such an environment makes the formation of defects very likely, we study defect effects on the electronic structure to explain the increased mobility. We find that Sn interstitials and O vacancies modify the valence band, inducing higher contributions of the delocalized Sn 5p orbitals as compared to the localized O 2p orbitals, thus increasing the mobility. This mechanism of valence band modification paves the way to a systematic improvement of transparent p-type semiconductors.

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

p-type tin monoxide (SnO) nanowire field-effect transistors with stable enhancement mode behavior and record performance are demonstrated at 160 °C. The nanowire transistors exhibit the highest field-effect hole mobility (10.83 cm2 V−1 s−1) of any p-type oxide semiconductor processed at similar temperature. Compared to thin film transistors, the SnO nanowire transistors exhibit five times higher mobility and one order of magnitude lower subthreshold swing. The SnO nanowire transistors show three times lower threshold voltages (−1 V) than the best reported SnO thin film transistors and fifteen times smaller than p-type Cu2O nanowire transistors. Gate dielectric and process temperature are critical to achieving such performance.

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200°C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm2V−1s−1, large memory window (∼16 V), low read voltages (∼−1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

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