Nonphotolithographic Nanoscale Memory Density Prospects

Abstract

Abstract-Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up selfassembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10 11 b/cm 2 with modest active power requirements under 0.6 W/Tb/s for random read operations.

Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration

“…It has been shown to significantly increase the transistor density of crossbar memory circuits [5,8]. However, we show that high crosspoint density does not translate into high transistor density for logic.…”

“…In a crossbar, the crossing of two nanowires forms a crosspoint, which may be independently configured to implement a FET (p-FET or n-FET) [6] or a diode [7]. While many have shown that nanowire crossbars compare favorably to their MOSFET counterparts for memory [5,8], it is unclear how they would compare to their MOSFET counterparts in implementing logic, which is our focus.…”

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

“…We adopt a model presented in [14] to estimate the area of nanoscale memory. Each bank in the memory is composed of a set of crossed nanoscale wires supported by a set of interface microscale wires.…”

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

“…In reference [3], the author improved the choice of materials and suggested a better design of the organic switch, claiming the elimination of the artifacts. The organization of the memory into smaller blocks and interfacing modules was presented in [7].…”