The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

Logic gates were fabricated from an array of configurable switches, each consisting of a monolayer of redox-active rotaxanes sandwiched between metal electrodes. The switches were read by monitoring current flow at reducing voltages. In the "closed" state, current flow was dominated by resonant tunneling through the electronic states of the molecules. The switches were irreversibly opened by applying an oxidizing voltage across the device. Several devices were configured together to produce AND and OR logic gates. The high and low current levels of those gates were separated by factors of 15 and 30, respectively, which is a significant enhancement over that expected for wired-logic gates.

Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easi,b route around defects, has significant implications for any future nanometerscale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system. T h e last 25 years have witnessed astonishing advances in the fields of microelectron--its and computation. The first integrated circuit mlcro~rocessor, the Intel 4004, was able to perform roughly 5000 binary-coded decimal additions per second with a total power consumption of about 10 W (-500 additions ver Joule) in 1971. whereas mod-. " , ern lnicroprocessors can perform -3 X 106 additions oer Joule. The 1997 National L , Technology Roadlnap for Semiconductors (1) calls for an additional factor of lo3 , . increase in the computational efficiency by the vear 2012. If this eoal is attained. then perfArmance of the silycon-based integrated circuit \+~11 have imoroved bv nearlv seven orders of magnitud; in 40 years, using energy consumed per operation as a metric, with a single manufacturing paradigm. Although co~nplelnentarymetal oxide semiconductor (CMOS) technology is predicted by many researchers to run into significant physical limitations shortly after 2010 (Z), the enerev cost of an addition ooeration -,\+rillstill be nowhere near any fundamental physical limit. A crude estimate of the energy required to add two 10-digit decimal numbers, based on a thermodynamic analysis of nonreversible Boolean logic steps (3, 4) is -100.k.T.ln(2), which implies that 3 x 10'%dditions per Joule can be performed at room temperature without any reversible steps. Thus, there are potentially eight orders of magnitude in colnputational energy efficiency in a nonreversible machine available bevond the limits of CMOS technology. To achieve these f~~rther advances will require a totally different type of computational machinery, but knowing that such a system is in principle possible provides a strong incentive to hunt for it. The requirement for inventing a new technology paradigm has created exciting research opportunities for physical and biological scientists as well as for electrical engineers. Indeed, much of the current interest in interdisciplinary research in areas such as nanofabric...

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO(2) as the switching material.