Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration

Dong, Mianxiong; Lin, Zhouchen

doi:10.1109/date.2008.4484895

Cited by 3 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…7b), is considered. We compare our models with the ones used in the literature [10][11][12][13]. Examining the numbers in Table 2, we see that the proposed wire-ground model overwhelms the compared models.…”

Section: Evaluation Of the Proposed Capacitor-resistor Models Givmentioning

confidence: 95%

“…For FET and four-terminal switch based arrays. We exploit wire and resistance specifications as well as substrate material types according to [11][12]. Resistance values of n-type and p-type nanowires with 10nm length and 1nm 2 cross-section area are selected as 10kΩ and 38.1 kΩ, respectively [12].…”

Section: Performance Analysis: Power Delay Areamentioning

confidence: 99%

“…However, as expected the integration comes with some challenges and the accuracy problems in performance modelling and analysis is one of the significant ones. Conventional resistor-capacitor models do not meet the needs of nanoarrays [10][11][12][13]. They generally neglect wiring resistors/capacitors including crosstalk capacitors with an assumption that their values are much smaller than those of device resistors/capacitors.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Morgül

Peker

Altun

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

In this study, we introduce an accurate capacitorresistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.

show abstract

Section: Evaluation Of the Proposed Capacitor-resistor Models Givmentioning

confidence: 95%

Section: Performance Analysis: Power Delay Areamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays

Morgül

Peker

Altun

2016

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

show abstract

“…Indeed, the achievable complementary logic density in a crossbar is O(n -1 ), where n is the number of nanowires in each of the orthogonal arrays and is referred to as the dimension of the nanowire crossbar. Moreover, the delay of a crossbar logic circuit is O(n) [11]. So, it's better to have a small nanowire crossbar.…”

Section: B Modifed Caen-bist Algorithmmentioning

confidence: 98%

Modified CAEN-BIST algorithm for better utilization of nanofabrics

Zamanlooy

Ayatollahi

2008

2008 International Conference on Electrical and Computer Engineering

View full text Add to dashboard Cite

In the last 40 years there has been an exponential increase in the number of transistors per processor. This increase has been according to Moore's law that predicted the number of transistors that could be placed on the chip would double every two years. However, there are some challenges like leakage currents, process variation, costs and reliability issues like NBTI and HCI that may result to the end of scaling. A solution to CMOS scaling problems is based on architectures that use nanoelectronic devices. The main problem with these devices is their high defect rates due to their bottom up assembly. The reconfigurability of these architectures enables them to manage the high amount of defects. So, to use these architectures the defects should be found and after that in the mapping phase the defective elements are configured around. One of the architectures based on nanoelectronic devices is the nanofabric architecture proposed by Goldstein and Budiu [3]. Different algorithms have been proposed for finding defect map of nanofabric. One of them is proposed by Brown and Blanton [2]. In this paper a modification in CAEN-BIST algorithm has been proposed which improves the nanoblock defect density, test time and utilization of nanoblocks.

show abstract