Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays

Abstract

Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (VT), which is enabled by our underlying technology. We define two types of multi-valued decoders and model the defects they undergo due to the VT variation. Multi-valued hot decoders yield better area saving than n-ary reflexive codes (NRC), and under severe conditions, NRC enables a non-vanishing part of the code space to recover. There are many combinations of decoder type and number of VT's yielding equal effective memory capacities. The optimal choice saves area up to 24%. We also show that the precision of the addressing voltages for decoders with unreliable VT's is a crucial parameter for the decoder design and permits large savings in memory area.

An Outlook on Design Technologies for Future Integrated Systems

“…The architecture of decoders for interfacing to nanoarrays is an important issue [12], [105]. All proposed solutions, either suggested as concepts [32], [56], [109], or implemented on real chips [8], rely on the principle of a linear array of transistors that can be aligned with the nanowires.…”

“…High-density decoding can be achieved by using multivalued logic to address the nanoarray (which can store binary or multivalued information). Moreover, the addressing scheme can be made robust against threshold voltage variations by using specific encoding scheme that exploit redundant information [12].…”

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories

“…Crossbar memories can be realized in a separate part of a standard CMOS chips, where a decoder bridges the two parts having different scales [13,16,3]. The variability affecting the nanowires causes decoder defects, where more than one bit can be addressed simultaneously [4]. Consequently, Pattern Sensitivity Faults (PSFs) with no neighborhood pattern are expected to be dominant in crossbar memories.…”

“…The mask-based [3] and random-contact [16] decoders were suggested for undifferentiated nanowires with no defined doping profile. A schematic principle of an array of nanowires with a decoder [4] is illustrated in Figure 1. The alternation of regions having different doping levels or different insulator types on every nanowire defines a pattern of field effect transistors (FET) with different threshold voltages (V T ), and the address of the nanowire.…”

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

“…The detection of code errors depends on the encoding and was investigated for the binary case in [2]. We presented this approach in [4] where we restricted our study to the advantages of MVL addressing within this technology. In this paper, we generalize the implementation of MVL to a wide range of other decoder technologies.…”