A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories

Abstract

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only ∼ 10 −4 , which can be also reduced further (up to ∼ 60×) by trading-off only ∼ 35% area overhead in the memory.

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

“…The obtained linearized stochastical current model was used in order to optimize the thresholder parameters I 0 and I 1 [10].…”

“…A tradeoff can be considered between the redundancy level involved, which represents additional area/power, and a reduction of the maximum critical path delay, which actually means possible increased operating frequency. Assuming that each gate in the critical path consists of six transistors, N cp D 10 4 , and that a whole chip has 4 10 8 transistors according to ITRS [10], replicating each critical path 3, 5, and 7 times causes an overhead of 0.8, 1.5, and 2.3% respectively. The maximum critical path delay distribution, including both WID and D2D variations, is analyzed for three technologies: one 65-nm commercial technology and two future technology nodes 45 and 32 nm.…”

“…The maximum critical path delay distribution, including both WID and D2D variations, is analyzed for three technologies: one 65-nm commercial technology and two future technology nodes 45 and 32 nm. Both the 45-and 32-nm technologies are hypothetical, and the parameters have been selected to anticipate a realistic set [10,18,[33][34][35][36].…”