Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Abstract

Abstract-The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, based on the existing technological solutions for threshold voltage differentiation of NW devices. This is equivalent to using a multivalued logic addressing scheme. With this approach, it is possible to reduce the decoder size and keep it defect tolerant. We formally define two types of multivalued codes (i.e., hot and reflexive codes), and we estimate their yield under high variability conditions. Multivalued hot decoders yield better area saving than n-ary reflexive codes, and under severe conditions, reflexive codes enable a nonvanishing part of the code space to randomly recover. The choice of the optimal combination of decoder type and logic level saves area up to 24%. We also show that the precision of the addressing voltages when a high variability affects the threshold voltages is a crucial parameter for the decoder design and permits large savings in memory area. Moreover, a precise knowledge about the variability level improves the design of memory decoders by giving the right optimal code.

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

“…A decoder is utilized in order to make every NW within this set uniquely addressable by the outer circuit. It is formed by a series of transistors along the NW body, controlled by the mesowires and having different threshold voltages [29], as shown in Fig. 1(b) and (c).…”

“…Using NWs doped with different doses and the same type (either n or p), the minimal cost is given by M = 2 · log 2 (N ) [29]. The minimal cost is just the half of this values, when a complementary logic (using both n-and p-type) is used; however, for technological reasons, this is not expected to be the case for NW decoders [29]. The randomness of stochastic approaches [30]- [32] results in a large overhead in M .…”

“…The factor n is chosen such that the width of every cave is matched by the lithographic dimensions, making the number of NWs in every cave in the range ∼3 × L l /L n . The factor three comes from the symmetry of the caves and the possible need for some overhead in order to bridge the lithographic and sublithographic dimensions [29]. For instance, at the 65-nm technology node (L l = 65 nm) and with 20-nm wide NWs (L n = 20 nm), n should be chosen such that every cave has ∼10 parallel NWs.…”

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique

“…A decoder is utilized in order to make every nanowire within this set uniquely addressable by the outer circuit. It is formed by a series of transistors along the nanowire body, controlled by the mesowires and having different threshold voltages (VT's) [2], as shown in Fig. 2(a) and 2(b).…”

“…7 for N = 10 show that Φ is constant for all binary codes and equal to the double of the number of nanowires in a half cave. Higher logic level was suggested as a way to reduce the area overhead of the decoder [2]. However, Fig.…”