Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Jamaa, M. Haykel Ben; Cerofolini, G. F.; Micheli, Giovanni De; Leblebici, Yusuf

doi:10.1109/tnano.2010.2089532

Cited by 6 publications

(5 citation statements)

References 40 publications

(75 reference statements)

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“…The SiNWs are then defined from the wafer by a typical etching step [ 44 , 45 ] using the pre-defined mask. For example, millimeter SiNWs can be readily fabricated on SOI wafers using an etched mask patterned from the engineered nano-cavity/undercut structures ( Figure 4 ) [ 44 , 46 , 47 ] or by transforming the vertical thickness of the masking materials into the lateral width of the nanowire patterns [ 41 , 48 , 49 , 50 , 51 ]. Applying this concept, well-ordered SiNWs can be patterned with any desired configurations ranging from sub-10 nm in width [ 46 ], millimeters or more in length [ 45 ] and with high density [ 44 ].…”

Section: Cmos-compatible Silicon Nanowire Fabrication Techniquesmentioning

confidence: 99%

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

et al. 2018

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Owing to their two-dimensional confinements, silicon nanowires display remarkable optical, magnetic, and electronic properties. Of special interest has been the development of advanced biosensing approaches based on the field effect associated with silicon nanowires (SiNWs). Recent advancements in top-down fabrication technologies have paved the way to large scale production of high density and quality arrays of SiNW field effect transistor (FETs), a critical step towards their integration in real-life biosensing applications. A key requirement toward the fulfilment of SiNW FETs’ promises in the bioanalytical field is their efficient integration within functional devices. Aiming to provide a comprehensive roadmap for the development of SiNW FET based sensing platforms, we critically review and discuss the key design and fabrication aspects relevant to their development and integration within complementary metal-oxide-semiconductor (CMOS) technology.

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Section: Cmos-compatible Silicon Nanowire Fabrication Techniquesmentioning

confidence: 99%

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

et al. 2018

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“…[22]. The process is based on the iterative definition of thin spacers with alternating semiconducting and insulating materials.…”

Section: Spacer-based Nanowire Arraysmentioning

confidence: 99%

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Ben-Jamaa¹,

Gaillardon²,

Clermidy³

et al. 2011

sci adv mat

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Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS.

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“…Over the past years, polysilicon nanowires (NWs) have been widely investigated for the potential applications like high performance surround gate polysilicon NW thin film transistors (TFT) [1][2][3][4], innovative memory devices [5][6][7][8], excellent thermoelectric performance [9][10][11] and for promising biosensing applications [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

“…Polysilicon nanowire has been shown to demonstrate a record low thermal conductivity [11] and also has been applied for high sensitivity, real-time and label-free detection of diverse biological targets like inflammatory biomarkers, DNAs, miRNAs, proteins, SARS-Co-V2 etc [12][13][14][15][16][17]. Polysilicon nanowires are usually realized by using thin film technology and spacer etch technique [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] (figure 1). Use of mature lithography and industry standard deposition/spacer etch techniques make this technology potentially attractive.…”

Section: Introductionmentioning

confidence: 99%

“…In this technology, polysilicon nanowires can be fabricated on glass or plastic substrates which may enable flexible foil electronics, affordable disposable diagnostics and portable, wearable and/or implantable sensors. However, no mask protection is used during spacer etch and hence, the dry etch plasma affects the corner of the nanowire thereby results in the quarter circle shaped NW and sidewall striations [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. As a result, it is difficult to control volume of the nanowire across the wafer and hence, the degraded uniformity may severely affect the manufacturability of the process.…”

Section: Introductionmentioning

confidence: 99%

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Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

Hakim

2023

Eng. Res. Express

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We report a low-cost mass manufacturable route for polysilicon nanowire (NW) fabrication through comparative investigations of spacer etch techniques to realize nanowires from amorphous silicon (α-Si) layer. The process uses thin film technology and mature top-down microelectronics (linewidth > 10 µm). Anisotropic deep silicon etch process using the elevated plasma density of high-density low-pressure systems (HDLP) with a simultaneous flow of etchant SF6 and inhibitor C4F8 delivered nanowires with quarter circle shape. The nanowires are also characterized with significant sidewall striations and noticeable aggregation of polymers. HDLP etch system with a sequential flow of etchant SF6 and inhibitor C4F8 delivered a near rectangular nanowire shape. However, the generally good profile is marred with significant sidewall striations and accumulation of polymers at the tip of the etched sidewall. Shallow etch process using low density plasma in a cheap capacitively coupled reactive ion etch (RIE) equipment with a simultaneous flow of etchant SF6 and inhibitor O2 delivered nanowires with ideal rectangular shape. The nanowires have hardly visible sidewall striations and/or polymer. These results indicate that deep silicon HDLP etch processes albeit advanced and costly are not suitable for good quality nanowire definition using spacer etch from a thin film of α-Si layer. Low density plasma process with simultaneous flow of SF6 and O2 gases in relatively cheap RIE system provides high quality nanowires and hence, provides a simple, low cost, wafer scale mass manufacturable route for high quality polysilicon nanowire fabrication.

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Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

Cited by 6 publications

References 40 publications

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

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