Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

Abstract

We report a low-cost mass manufacturable route for polysilicon nanowire (NW) fabrication through comparative investigations of spacer etch techniques to realize nanowires from amorphous silicon (α-Si) layer. The process uses thin film technology and mature top-down microelectronics (linewidth > 10 µm). Anisotropic deep silicon etch process using the elevated plasma density of high-density low-pressure systems (HDLP) with a simultaneous flow of etchant SF6 and inhibitor C4F8 delivered nanowires with quarter circle shape. The nanowires are also characterized with significant sidewall striations and noticeable aggregation of polymers. HDLP etch system with a sequential flow of etchant SF6 and inhibitor C4F8 delivered a near rectangular nanowire shape. However, the generally good profile is marred with significant sidewall striations and accumulation of polymers at the tip of the etched sidewall. Shallow etch process using low density plasma in a cheap capacitively coupled reactive ion etch (RIE) equipment with a simultaneous flow of etchant SF6 and inhibitor O2 delivered nanowires with ideal rectangular shape. The nanowires have hardly visible sidewall striations and/or polymer. These results indicate that deep silicon HDLP etch processes albeit advanced and costly are not suitable for good quality nanowire definition using spacer etch from a thin film of α-Si layer. Low density plasma process with simultaneous flow of SF6 and O2 gases in relatively cheap RIE system provides high quality nanowires and hence, provides a simple, low cost, wafer scale mass manufacturable route for high quality polysilicon nanowire fabrication.