Abstract

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quaddedtransistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quaddedtransistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

Abstract-We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques.

Abstract-In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost. We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS'85 benchmark circuits synthesized into smaller sized LUTs.

We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, we implement a combined two dimensional coding scheme using Hamming and BCH codes to address fault rates greater than 5%. In the second technique, Hamming coding is complemented with Bad Line Exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20%). We have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don't Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.