Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged, and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolution neural networks (CNNs) have demonstrated their effectiveness in image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve desired performance levels. Consequently, hardware accelerators that use application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and graphic processing units (GPUs) have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism as well as due to their energy efficiency. In this paper, we review recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in FPGA-based accelerators of deep learning networks. Thus, this review is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

No abstract

No abstract

No abstract

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this paper, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.

Abstract

No abstract

Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit. Index Terms-Combinationalcircuit reliability, fault tolerance, single event transient, single event upset, soft errors. ACRONYMS AND ABBREVIATIONS SET single-event transient SEU single-event upset FX fast extraction CMOS complementary metal oxide semiconductor SER soft error rate TMR triple modular redundancy HICC history index of correct computation CDC controllability don't-care condition Vdd voltage drain-to-drain GND ground Manuscript