2003
DOI: 10.1145/944027.944030
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Test vector decomposition-based static compaction algorithms for combinational circuits

Abstract: Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this paper, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is pr… Show more

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Cited by 45 publications
(27 citation statements)
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“…In Independent Fault Clustering (IFC) [1,2], Independent Fault Sets (IFSs) with respect to a given test set are first derived. Two faults are independent if they are not detected by the same test vector.…”
Section: Proposed Test Compaction Techniquementioning
confidence: 99%
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“…In Independent Fault Clustering (IFC) [1,2], Independent Fault Sets (IFSs) with respect to a given test set are first derived. Two faults are independent if they are not detected by the same test vector.…”
Section: Proposed Test Compaction Techniquementioning
confidence: 99%
“…In static test compaction, the number of test vectors is reduced after they are generated, whereas in dynamic test compaction, the number of test vectors is minimized during the automatic test pattern generation (ATPG) process. Static test compaction algorithms for combinational circuits can be divided into three broad categories [1]: (1) Redundant vector elimination, (2) Test vector modification, and (3) Test vector addition and removal. In the first category, compaction is performed by dropping redundant test vectors.…”
Section: Introductionmentioning
confidence: 99%
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