Modeling of DMOS subjected to fast temperature cycle stress and improvement by a novel metallization concept

Smorodin, T.; Wilde, Juergen; Nelle, P.; Lilleodden, Erica T.; Stecher, M.

doi:10.1109/relphy.2008.4558990

Cited by 11 publications

(5 citation statements)

References 4 publications

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“…3, the microcompression technique consists of pushing on µm-diameter posts milled by focused ion beam (FIB) and monitoring the resulting load-displacement response using a nanoindenter with suitable tip [5], [6]. Stress-strain curves as those shown in Fig.…”

Section: Microcompression Methodsmentioning

confidence: 99%

“…It has been used to characterize a wide variety of materials, brittle and ductile, and evolved to a stage where wafer-scale measurements are possible [4]. Concerning the microcompression method, microposts composed of the films of interest are machined and force-displacement data are recorded as the structures are loaded in the normal direction [5], [6]. The microtensile test relies on a micromachined Si test structure composed of fixed and movable parts whose design allows the uniform, uniaxial elongation of bridging specimens when displacements are imposed to the inner movable frames.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Mechanical characterization of CMOS metal layers

Gaspar

Smorodin

Schmidt

et al. 2009

TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference

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This paper reports on the strain rate dependence of the mechanical properties of aluminum-based metallization layers. Evaporated Al, sputtered Al 99% Cu 1% , and multilayers of µm-thick Al 99% Cu 1% films separated by thinner TiN/Ti layers are characterized using the bulge test, the microcompression method and the microtensile technique. Elastic, ductile and fracture parameters are extracted for strain rates dε/dt between 10 -4 to 10 1 s -1 . The Young's modulus E of sputtered layers, 59 GPa, is marginally lower than that of evaporated films, 63 GPa. Both fracture strain ε max and strength σ max of sputtered Al, 5.5% and 79 MPa, respectively, show no significant variation with dε/dt, changing to ε max = 2.1 % and σ max = 200 MPa when such films are stacked with TiN/Ti layers. Regarding evaporated Al, the failure parameters depend strongly on the strain rate: ε max decreases from 33.2 to 1.3% and σ max increases from 153 to 380 MPa within the entire range of tested dε/dt values.

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Section: Microcompression Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mechanical characterization of CMOS metal layers

Gaspar

Smorodin

Schmidt

et al. 2009

TRANSDUCERS 2009 - 2009 International Solid-State Sensors, Actuators and Microsystems Conference

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“…The dashed lines in Figure 3 [14]. So generally a smaller layer thickness of the aluminum layers is desirable if the IC has to withstand repetitive thermal cycling.…”

Section: Figure 3: Coffin-manson Chart Of Mean Lifetime (T63 Value) Bmentioning

confidence: 99%

Low-cycle fatigue of multilayer metal stack employed as fast wafer level monitor for backend integrity in smart power technologies

Mann

Lohmeyer

Joseph

2016

2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and

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A novel approach for wafer-level test and monitoring of multilayer metal-stack integrity in integrated circuit process technology based on the low-cycle fatigue of power device metallization structure is described. Repetitive power pulsing at the limit of the electro-thermal safe-operating area of the devices reveals systematic changes in level and homogeneity of intrinsic thermomechanical robustness and is able to activate latent defects. Exemplarily for two smart-power process technologies the intrinsic low-cycle lifetime limit is explored as reference basis and transfer to test vehicles on product or process control module is validated in experimental case-study and supported by detailed electrothermal simulation of stress pulse events.

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“…In addition, we showed in [3] that the reliability is highly affected by the temperature distribution (temperature gradients). The reliability of power devices can be improved by optimizing the layout of the DMOS metallization system [4], by using materials with better thermal/mechanical properties [5][6] or by controlling both the peak temperature and the temperature gradient in the device [3].…”

Section: Imd Crackingmentioning

confidence: 99%

Reliability characterization of power devices which operate under power cycling

Simon

Boianceanu

Mey

et al. 2015

2015 International Semiconductor Conference (CAS)

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The safe-operating-area (SOA) of automotive DMOS transistors, which are operated repeatedly under high power pulses (power cycling), is lower than the classical singlepulse SOA and it is dependent on the geometry of the transistor. In this paper, we present a test system for reliability characterization of power devices, of various geometries, which operate under power cycling conditions. INTRODUCTIONAutomotive smart-power switches are used in powertrain applications (e.g. engine management) to drive actuators which have an inductive behavior (relays, valves) or a capacitive behavior (light bulbs). Often, the switching element is a DMOS (double-diffused MOS) transistor. These devices are subject to elevated junction temperatures, caused by self-heating, during high power transients generated while driving inductive or capacitive loads. While operated repetitively under high power events (power cycling), the reliability of the whole chip can be affected by cracks in the DMOS metallization system due to thermo-mechanical effects [1]. Mechanical stresses accumulate with each power cycle, until fracture of inter-metal dielectric (IMD) occurs, which is followed by short-circuit of nearby metal lines [2].

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Modeling of DMOS subjected to fast temperature cycle stress and improvement by a novel metallization concept

Cited by 11 publications

References 4 publications

Mechanical characterization of CMOS metal layers

Mechanical characterization of CMOS metal layers

Low-cycle fatigue of multilayer metal stack employed as fast wafer level monitor for backend integrity in smart power technologies

Reliability characterization of power devices which operate under power cycling

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