DMOS transistors for power applications dissipate significant amount of energy, leading to substantial selfheating. Thus appears the necessity of DMOS characterization at high temperatures. In this paper we present a test structure, with integrated heating elements, used for device characterization up to 500ºC.
Abstract-In automotive applications, the lifetime of the power transistors is limited by the number of power pulses, induced by, e.g., short-circuit or inductive clamping events. This letter presents a solution for reliability improvement of double-diffused metal-oxide-semiconductor transistors which operate under thermomechanical stresses generated during power cycling.
The safe-operating-area (SOA) of automotive DMOS transistors, which are operated repeatedly under high power pulses (power cycling), is lower than the classical singlepulse SOA and it is dependent on the geometry of the transistor. In this paper, we present a test system for reliability characterization of power devices, of various geometries, which operate under power cycling conditions.
INTRODUCTIONAutomotive smart-power switches are used in powertrain applications (e.g. engine management) to drive actuators which have an inductive behavior (relays, valves) or a capacitive behavior (light bulbs). Often, the switching element is a DMOS (double-diffused MOS) transistor. These devices are subject to elevated junction temperatures, caused by self-heating, during high power transients generated while driving inductive or capacitive loads. While operated repetitively under high power events (power cycling), the reliability of the whole chip can be affected by cracks in the DMOS metallization system due to thermo-mechanical effects [1]. Mechanical stresses accumulate with each power cycle, until fracture of inter-metal dielectric (IMD) occurs, which is followed by short-circuit of nearby metal lines [2].
DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures. This can lead to device failure and reduced lifetime. Hence, numerical electro-thermal simulations already during circuit design are used to ensure that the device temperature stays within the accepted range. In such simulations, the influence of the on-chip metallization must be considered correctly. Therefore, accurate temperature measurements for different on-chip metallization configurations are required for simulator calibration.In this paper, we present test structures with different metal layers and via configurations suitable for that purpose. We will discuss how accurate results can be obtained that show even very small differences between structures with a similar thermal behavior. The measurement results, combined with numerical simulations, give also valuable insights into the heat removal capability of the on-chip metallization.
The emerging smart power BCD technologies allow smaller device sizes hence, under the same operating conditions, the device must dissipate the same amount of power on a much smaller area, which leads to a more pronounced self -heating effect. Therefore, accurate prediction of heat dissipation in the DMOS structure, up to thermal runaway, is necessary. We have designed a test structure capable of uniformly heating a small area VDMOS device up to 500°C. In this paper we validate the test structure by modeling the behavior of the DMOS transistor up to very high temperatures.
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