Low-cycle fatigue of multilayer metal stack employed as fast wafer level monitor for backend integrity in smart power technologies

Abstract

A novel approach for wafer-level test and monitoring of multilayer metal-stack integrity in integrated circuit process technology based on the low-cycle fatigue of power device metallization structure is described. Repetitive power pulsing at the limit of the electro-thermal safe-operating area of the devices reveals systematic changes in level and homogeneity of intrinsic thermomechanical robustness and is able to activate latent defects. Exemplarily for two smart-power process technologies the intrinsic low-cycle lifetime limit is explored as reference basis and transfer to test vehicles on product or process control module is validated in experimental case-study and supported by detailed electrothermal simulation of stress pulse events.