Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Andrieu, F.; Weber, O.; Mazurier, J.; Thomas, Olivier; Noël, J.‐P.; Fenouillet-Béranger, C.; Mazellier, Jean-Paul; Perreau, P.; Poiroux, T.; Morand, Y.; Morel, T.; Allegret, S.; Loup, V.; Barnola, S.; Martín, F.; Damlencourt, J.-F.; Servin, Isabelle; Cassé, M.; Garros, X.; Rozeau, O.; Jaud, M.-A.; Cibrario, G.; Cluzel, J.; Toffoli, A.; Allain, F.; Kies, R.; Lafond, D.; Delaye, V.; Tabone, C.; Tosti, L.; Brévard, L.; Gaud, P.; Paruchuri, Vamsi; Bourdelle, K.K.; Schwarzenbach, W.; Bonnin, Olivier; Nguyen, B.-Y.; Doris, B.; Bœuf, F.; Skotnicki, T.; Faynot, O.

doi:10.1109/vlsit.2010.5556122

Cited by 75 publications

(30 citation statements)

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“…This increasing variability is brought on by continued scaling and by the emergence of an increasing number of atomistic phenomena like random dopant fluctuations and line edge roughness. While there are some upcoming technology innovations that promise some relief, like FinFETs or thin-body SOI devices [16], [17], the overall trend is likely to continue through the end of the Silicon CMOS era.…”

Section: Discussionmentioning

confidence: 99%

Goldilocks failures: Not too soft, not too hard

Nassif

Kleeberger

Schlichtmann

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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It is well known that circuits fail when one or more of the constituent components fails, due -for example-to phenomena such as electromigration in wires. Such hard failures, typically due to topological changes in circuit connectivity, are treated distinctly from soft failures which could be due to components drifting out of spec over time. However, in certain types of circuits, such as memory, the distinction between soft and hard failures is not clearly defined. The primary cause of the blurring between these two phenomena is manufacturing variability, which can make a topologically correct circuit behave as if it had a short or an open. This paper will show the linkage between these two failure types, and show how increasing variability in future technologies will likely exacerbate this problem further.

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Section: Discussionmentioning

confidence: 99%

Goldilocks failures: Not too soft, not too hard

Nassif

Kleeberger

Schlichtmann

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…Thus, the thicker the buried oxide, the higher the source to drain coupling will be. Scaling down of the buried oxide is mandatory to maintain the electrostatic characteristics of MOSFETs (Figure 6(a)) [25][26][27][28]. Recent results have shown that [29,30]; (b) strained dual channel CMOS process flow [29].…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

“…buried oxide could be scaled to 10 nm on large 300 mm diameter wafers with Si layers as thin as 6 nm [25][26][27][28]. The control of such substrates could lead to multi-threshold control.…”

Section: Fully Depleted Devices On Insulator Ultra-thin Silicon Thickmentioning

confidence: 99%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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“…To meet these requirements in CMOS technology and to avoid additional oxide thickness and channel length scaling related issues, new device architectures such as FinFET and FDSOI have been proposed to replace the planar bulk CMOS technology [1][2]. Lower threshold voltage variability, better control of the channel, and compatibility with standard planar CMOS technology makes fully depleted silicon-on-insulator (FD-SOI) an attractive option [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Theodorou

Ioannidis

Haendler

et al. 2015

2015 IEEE International Reliability Physics Symposium

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A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

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Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Cited by 75 publications

References 0 publications

Goldilocks failures: Not too soft, not too hard

Goldilocks failures: Not too soft, not too hard

Ultra-thin films and multigate devices architectures for future CMOS scaling

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

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