No abstract

No abstract

No abstract

No abstract

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and (b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V th , T ox and R s .If P is constant within a die, but varies within a wafer or lot, then P is independent of local differences within the chip, thus variations in P may be treated as noise imposed upon the circuit, and analyzed using worst-case or Monte-Carlo analysis. In this case, it is necessary to have only the distribution describing P to estimate the performance variation in the design.If P varies within a die because (a) the die is large relative to the wafer, or (b) P has a strong layout dependence (e.g., nested vs. isolated effect [3]). Determining the design performance variation becomes harder because the number of entities varying is larger [4,5].Consider the canonical circuit in Figure 22.4.1 composed of a source buffer driving an identical destination buffer through a length of minimum-width wire. Examine the relative impact of wire and device variability on the delay for various technology generations. Across technologies the W/L ratio is maintained for the buffer and the maximum wire length is found beyond which inserting a buffer between the source and destination would lower overall delay [6]:where τ B , R B and C B are the delay, output resistance and input capacitance of the buffer, and R w and C w are per unit length of the wire. Five technologies in the 250 to 70nm gate length range conforming to the 1997 Semiconductor Industry Association (SIA) technology roadmap are considered, and L max is computed [6]. The results are shown in Figures 22.4.4 and 22.4.2, which explains the wire geometrical parameters. Figure 22.4.3 shows a superlinear (relative to L eff ) decrease in the length L max vs. process generation, which shows an increase in the influence of interconnect.The impact of device and wire variations on delay of the buffer/wire combination is then considered, assuming tolerances conforming broadly to SIA roadmap numbers with some exceptions based on early experience with the technologies (Figure 22.4.5). Figure 22.4.3 shows the tolerances expressed as percentages, which more clearly shows the current trends in the various components. The contributions of of device and wire variability to total delay variability remain fairly constant which is interesting because it means that this canonical circuit is a good gauge to differentiate circuits based on their sensitivity to device and wire variations ( Figure 22.4.6). If similar simulations are performed (A) without scaling transistor widths, or (B) scaling wire length at the same rate as L eff , results are very different.The impact of within-die variability of device parameters is well studied but wire variability has only recently been studied [5,8]. This is difficult because within-die var...