High-performance CMOS variability in the 65-nm regime and beyond

Bernstein, K.; Frank, D.J.; Gattiker, A.; Haensch, Wilfried; Ji, B.L.; Nassif, Sani R.; Nowak, E.; Pearson, D.J.; Rohrer, Norman J.

doi:10.1147/rd.504.0433

Cited by 438 publications

(246 citation statements)

References 44 publications

Supporting

Mentioning

239

Contrasting

Unclassified

Order By: Relevance

“…Therefore, the average number of dopant atoms in the nano-scaled MOSFET approaches only few tens of impurities [17] and its standard deviation is not negligible. However, it significantly contributes to the total random V TH variation.…”

Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

show abstract

Section: Random Dopant Fluctuation (Rdf)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…Global variations of the nMOS and pMOS threshold voltages are denoted as ΔV thn and ΔV thp , respectively. We assume the global variability follows a normal distribution as reported in [8], and the standard deviation of the normal distribution is 26.7 mV. We set the ranges of the global variations are from −80 to +80 mV, for both ΔV thn and ΔV thp .…”

Section: Parameter Estimation Flowmentioning

confidence: 99%

“…Global variations are deviations from a target value, which is common to all transistors within a chip. The global variation component can also be considered as an offset of a parameter calculated as an average over a chip [8], [9]. Local variations, in contrast, manifest themselves at the device-level fluctuation and vary independently from device to device.…”

Section: Introductionmentioning

confidence: 99%

Device-Parameter Estimation through IDDQ Signatures

Shintani

Satō

2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYWe propose a novel technique for the estimation of deviceparameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

show abstract

“…Other options are being explored as alternatives, which include semiconductor nanowire (SNW) based FETs [11][12][13], FETs comprised of 2D materials [14,15], and FETs with sophisticated gate structures [16], such as multiple independent gates [5,6] or a gate with embedded ferroelectric material [17]. There is, however, no clear pathway for overcoming a FET's intrinsic physical limitations [18][19][20] dictated by its operation mechanism, such as random dopant fluctuations [3] and gate fabrication complexities [21], and no viable rival technology currently exists. We offer a competitive alternative with additional unique functionalities.…”

Section: Introductionmentioning

confidence: 99%

Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

et al. 2016

View full text Add to dashboard Cite

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g., field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore's law to the quantum region without requiring a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to ∼1.0 × 10 6 with a source-drain voltage of ∼1.43 V, gate-power of ∼260 nW, and a subthreshold swing of ∼0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

show abstract

High-performance CMOS variability in the 65-nm regime and beyond

Cited by 438 publications

References 44 publications

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Device-Parameter Estimation through IDDQ Signatures

Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

Contact Info

Product

Resources

About