The work-function variation (WFV) in high-κ/ metal-gate (HK/MG) Ge-source tunnel FETs (TFETs) is evaluated using technology computer-aided design simulations. By matching the simulation results with the plot for the ratio of the average grain size to the gate area (i.e., the RGG plot), we find that the slope in the RGG plot for the TFET can be significantly altered depending on three main factors, namely, the gate width, average grain size, and equivalent oxide thickness. In addition, it is verified that the variation of channel potential affects the WFV-induced threshold voltage variation in HK/MG Ge-source TFETs.
A cascaded bidirectional distributed gain amplifier (BDGA) with asymmetrical stages has been reported. By cascading two unit BDGAs using a common source (CS) stage in the middle, the BDGA benefits the multiplicative gain enhancement while it can still achieve a wide bandwidth owing to the distributed nature of the two BDGAs. Each gain stage of the BDGA is composed of the CS output stage to enhance the linearity in parallel with the cascode input stage to improve noise performance by providing higher gain. The proposed circuit architecture is fabricated in a 65 nm CMOS. The measurements exhibit a gain of 10.5 dB, and the 3‐dB bandwidth from 5.8 to 17.6 GHz. The measured output P1dB is 6.8 dBm along with 9.3 dBm of the saturated output power at 10 GHz. The circuit draws 75 mA from a 1.2 V supply and occupies 1.1 × 0.6 mm2 of the chip area.
We present an X-band bi-directional transmit/receive module (TRM) for a phased array system utilized in radar-based sensor systems. The proposed module, comprising a 6-bit phase shifter, a 6-bit digital step attenuator, and bi-directional gain amplifiers, is fabricated using 65-nm CMOS technology. By constructing passive networks in the phase-shifter and the variable attenuator, the implemented TRM provides amplitude and phase control with 360° phase coverage and 5.625° as the minimum step size while the attenuation range varies from 0 to 31.5 dB with a step size of 0.5 dB. The fabricated T/R module in all of the phase shift states had RMS phase errors of less than 4° and an RMS amplitude error of less than 0.93 dB at 9–11 GHz. The output 1dB gain compression point (OP1dB) of the chip was 5.13 dBm at 10 GHz. The circuit occupies 3.92 × 2.44 mm2 of the chip area and consumes 170 mW of DC power.
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