Study of High-$k$/Metal-Gate Work Function Variation in FinFET: The Modified RGG Concept

Nam, Hyohyun; Shin, Changhwan

doi:10.1109/led.2013.2287283

Cited by 26 publications

(18 citation statements)

References 9 publications

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“…WFV is generally dependent on two factors: (i) average grain size of gate material and (ii) gate area. Contrary to the case of the planar bulk MOSFET, the front-and back-gate effective areas in the SegFET are extended by about two times because of the EGA effect [29]. Therefore, each stripe in the SegFET has a greater gate area (i.e., planar bulk MOSFET: 25 × 32 nm 2 versus SegFET: 45 × 32 nm 2 ), so that the SegFET has a lower RGG resulting in the lower WFV.…”

Section: Variation-robust Advanced Device Structuresmentioning

confidence: 99%

“…Two face-to- face (i.e., front and back) gates in the FinFET mutually interact when building up an inversion layer or channel, so that the new grains in these gates will be generated with a new probability and work-function. Hence, a modified method for FinFET RGG calculation should consider the extended gate area (EGA) generated by these gates [29]. Correspondingly, the total gate area over which to calculate the FinFET RGG should be defined as: [{W gate + (4 × H fin )} × L gate ].…”

Section: Work-function Variation (Wfv)mentioning

confidence: 99%

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Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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Section: Variation-robust Advanced Device Structuresmentioning

confidence: 99%

Section: Work-function Variation (Wfv)mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

Self Cite

View full text Add to dashboard Cite

show abstract

“…In other words, a new WFV evaluation index that people can easily refer to is necessary. In order to achieve simplicity and accuracy in estimating the WFVinduced V TH variation, a new WFV evaluation index is introduced in [20,21]. The Ratio of average Grain size to Gate area (RGG), which is equal to {average grain size in the unit of nm} times {(channel length Â channel width)…”

Section: Random Variation Iii: Work-function Variation (Wfv)mentioning

confidence: 99%

“…8). In other words, the method to calculate the FinFET RGG should consider the extended gate area (EGA) generated by these gates [21]: the total gate area 3 Silicon device scaling scenario Fig. 9 depicts the history and future of CMOS silicon device technology.…”

Section: Random Variation Iii: Work-function Variation (Wfv)mentioning

confidence: 99%

State-of-the-art silicon device miniaturization technology and its challenges

Shin

2014

IEICE Electron. Express

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Complementary Metal-Oxide-Semiconductor (CMOS) process and silicon device technologies have progressed dramatically in the last 950 years. The achievements of semiconductor industry have dramatically improved the human lifestyle making it smarter. One of the biggest factors in this change is the continued CMOS scaling. However, at sub-30-nm CMOS technology nodes, one of the main technical barriers for reducing the size of CMOS silicon devices is the parametric failure caused by random variations such as line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). This paper discusses these issues in terms of (1) the physical understanding and quantitative evaluation of each random variation source, and (2) the technical solutions to address each of these random variation issues. Lastly, the silicon device scaling scenario from the past, the present and through to the future (i.e., 90 nm technology down to sub-10-nm technology) is briefly discussed.

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“…Note that the average grain size of the metal gate material (i.e., TiN) is 22 nm and that the grain sizes follow the Rayleigh distribution [11]. In modeling the WFV in the SegFETs, the extended gate area (EGA) [12] must be included when estimating the WFV value, because of the quasi-planar tri-gate device structure. Two-hundred samples for the WFV simulations were taken for both devices; the results are shown in Fig.…”

Section: Variation-immunity Analysismentioning

confidence: 99%

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation

Nam¹,

Park²,

Shin³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Segmented-channel MOSFETs (SegFETs) can achieve both good performance and variation robustness through the use of HfO 2 (a high-k material) to create the shallow trench isolation (STI) region and the very shallow trench isolation (VSTI) region in them. SegFETs with both an HTI region and a VSTI region (i.e., the STI region is filled with HfO 2 , and the VSTI region is filled with SiO 2 ) can meet the device specifications for high-performance (HP) applications, whereas SegFETs with both an STI region and a VHTI region (i.e., the VSTI region is filled with HfO 2 , and the STI region is filled with SiO 2 ) are best suited to low-standby power applications. AC analysis shows that the total capacitance of the gate (C gg ) is strongly affected by the materials in the STI and VSTI regions because of the fringing electric-field effect. This implies that the highest C gg value can be obtained in an HTI/VHTI SegFET. Lastly, the three-dimensional TCAD simulation results with three different random variation sources [e.g., line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV)] show that there is no significant dependence on the materials used in the STI or VSTI regions, because of the predominance of the WFV.

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Study of High-$k$/Metal-Gate Work Function Variation in FinFET: The Modified RGG Concept

Cited by 26 publications

References 9 publications

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Analysis of Random Variations and Variation-Robust Advanced Device Structures

State-of-the-art silicon device miniaturization technology and its challenges

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation

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Study of High-$k$/Metal-Gate Work Function Variation in FinFET: The Modified RGG Concept

Cited by 26 publications

References 9 publications

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Analysis of Random Variations and Variation-Robust Advanced Device Structures

State-of-the-art silicon device miniaturization technology and its challenges

Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO2or SiO2Trench Isolation

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Product

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Performance and Variation-Immunity Benefits of Segmented-Channel MOSFETs (SegFETs) Using HfO₂or SiO₂Trench Isolation