Delay variability: sources, impacts and trends

Abstract

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and (b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V th , T ox and R s .If P is constant within a die, but varies within a wafer or lot, then P is independent of local differences within the chip, thus variations in P may be treated as noise imposed upon the circuit, and analyzed using worst-case or Monte-Carlo analysis. In this case, it is necessary to have only the distribution describing P to estimate the performance variation in the design.If P varies within a die because (a) the die is large relative to the wafer, or (b) P has a strong layout dependence (e.g., nested vs. isolated effect [3]). Determining the design performance variation becomes harder because the number of entities varying is larger [4,5].Consider the canonical circuit in Figure 22.4.1 composed of a source buffer driving an identical destination buffer through a length of minimum-width wire. Examine the relative impact of wire and device variability on the delay for various technology generations. Across technologies the W/L ratio is maintained for the buffer and the maximum wire length is found beyond which inserting a buffer between the source and destination would lower overall delay [6]:where τ B , R B and C B are the delay, output resistance and input capacitance of the buffer, and R w and C w are per unit length of the wire. Five technologies in the 250 to 70nm gate length range conforming to the 1997 Semiconductor Industry Association (SIA) technology roadmap are considered, and L max is computed [6]. The results are shown in Figures 22.4.4 and 22.4.2, which explains the wire geometrical parameters. Figure 22.4.3 shows a superlinear (relative to L eff ) decrease in the length L max vs. process generation, which shows an increase in the influence of interconnect.The impact of device and wire variations on delay of the buffer/wire combination is then considered, assuming tolerances conforming broadly to SIA roadmap numbers with some exceptions based on early experience with the technologies (Figure 22.4.5). Figure 22.4.3 shows the tolerances expressed as percentages, which more clearly shows the current trends in the various components. The contributions of of device and wire variability to total delay variability remain fairly constant which is interesting because it means that this canonical circuit is a good gauge to differentiate circuits based on their sensitivity to device and wire variations ( Figure 22.4.6). If similar simulations are performed (A) without scaling transistor widths, or (B) scaling wire length at the same rate as L eff , results are very different.The impact of within-die variability of device parameters is well studied but wire variability has only recently been studied [5,8]. This is difficult because within-die var...

Physically clustered forward body biasing for variability compensation in nanometer CMOS design

“…Major challenges come from parametric variation (intra and inter die variation of channel length, oxide thickness, doping concentration etc) [1], increased power-density leading to higher chip temperatures and circuit aging [3]. These phenomena have a direct and profound impact on system performance resulting in parametric yield loss and reduced system lifetime.…”

Robust gate sizing by geometric programming

“…To use the spatial correlation model, we first place the circuits using the placement tool Capo [18], and then divide the chip area into different number of grids, depending on the circuit size, so that each grid size is of the order of 60µ × 60µ. We define σ ref as the vector of maximum percentage deviations from the nominal values of W and L. The elements of σ ref predicted from [15], are 25% of nominal width value and 20% of nominal channel length value. To calculate the elements of P matrix, we choose the value of σi = Kσ ref i , where K is a constant ≤ 1.…”

“…As will be explained in Section 4, we use this fact to incorporate the spatial correlations between the random parameter variations. To generate the uncertainty ellipsoid region, it is not required to make any assumptions about the distributions of the W and L. The only inputs needed to generate the P matrix are the standard deviations of the components of X, which can be empirically calculated [15], and correlation factors between the components of X, which can be derived from a spatial correlation model such as the ones used in [13] and [14].…”

Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation

“…P ROCESS-INDUCED variability has huge impacts on the circuit performance in the sub-90nm VLSI technologies [10], [9]. One important aspect of the variations comes from the chip leakage currents.…”

“…So, if we model V th or L as the random variables with Gaussian variations due to interdie or intra-die process variations, then the leakage currents will have a log-normal distribution as shown in [12]. On top of this, those random variables are spatially correlated within a die, due to the nature of the many physical and chemical manufacture processes [9].…”