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We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown. Index Terms-Dielectric breakdown, hard breakdown, leakage currents, MOS devices, oxide reliability, soft breakdown, SRAM.

Interface dermatitis includes diseases in which the primary pathology involves the dermo-epidermal junction. The salient histological findings include basal cell vacuolization, apoptotic keratinocytes (colloid or Civatte bodies), and obscuring of the dermo-epidermal junction by inflammatory cells. Secondary changes of the epidermis and papillary dermis along with type, distribution and density of inflammatory cells are used for the differential diagnoses of the various diseases that exhibit interface changes. Lupus erythematosus, dermatomyositis, lichen planus, graft versus host disease, erythema multiforme, fixed drug eruptions, lichen striatus, and pityriasis lichenoides are considered major interface diseases. Several other diseases (inflammatory, infective, and neoplastic) may show interface changes.

Resistive random access memory (RRAM) is a promising technology for energy-efficient neuromorphic accelerators. However, when a pretrained deep neural network (DNN) model is programmed to an RRAM array for inference, the model suffers from accuracy degradation due to RRAM nonidealities, such as device variations, quantization error, and stuck-at-faults. Previous solutions involving multiple readverify-write (R-V-W) to the RRAM cells require cell-by-cell compensation and, thus, an excessive amount of processing time. In this article, we propose a joint algorithm-design solution to mitigate the accuracy degradation. We first leverage knowledge distillation (KD), where the model is trained with the RRAM nonidealities to increase the robustness of the model under device variations. Furthermore, we propose random sparse adaptation (RSA), which integrates a small on-chip memory with the main RRAM array for postmapping adaptation. Only the on-chip memory is updated to recover the inference accuracy. The joint algorithm-design solution achieves the state-of-the-art accuracy of 99.41% for MNIST (LeNet-5) and 91.86% for CIFAR-10 (VGG-16) with up to 5% parameters as overhead while providing a 15-150× speedup compared with R-V-W. INDEX TERMS Convolution neural networks, device nonidealities, model robustness, neuromorphic computing, random sparse adaptation (RSA), resistive random access memory (RRAM).