High Speed Through Silicon Via Filling by Copper Electrodeposition

Kondo, Kazuo; Suzuki, Y.; Saito, Takeyasu; Okamoto, Naoki; Takauchi, Minoru

doi:10.1149/1.3313451

Cited by 61 publications

(37 citation statements)

References 4 publications

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“…8,9 In addition, the convection dependent adsorption of leveler can make a steep gradient of surface coverage. [10][11][12] This disproportion of leveler adsorption results in the local enhancement of Cu growth at the bottom of a filling feature. The growing surfaces from the side wall meet each other, zipping up the features from the bottom, which is represented by V-shaped profile of Cu deposit.…”

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confidence: 99%

Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor

Kim

Choe

et al. 2013

J. Electrochem. Soc.

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A method is introduced for Cu bottom-up filling at trenches with dimensions similar to those of through silicon via in the presence of three organic additives. The electrodeposition is galvanostatically conducted, and the potential-time curves during the gap-filling and the evolution of deposition profiles according to the deposition time are investigated to clarify the mechanism of the Cu bottom-up filling. The role of each organic additive is examined by electrochemical analyses and the gap-filling profiles with various combinations of organic additives. Based on the results, the gap-filling mechanism regarding the surface coverages of organic additives is suggested. The bottom-up filling of Cu is achieved with the establishment of growing surface at the bottom of trench via the accumulation of accelerator and the strong obstruction of Cu reduction at the side wall and top surface by inhibiting adsorbates. Trenches with 40 μm depth and widths of 6 or 8 μm are filled using the suggested mechanism within 15 min.

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confidence: 99%

Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor

Kim

Choe

et al. 2013

J. Electrochem. Soc.

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“…We have already reported that 10 μm diameter via of aspect ratio of 7.0 is perfectly filled within 37 minutes by using diallylamine leveler and oxygen gas bubbling (8,(12)(13)(14). By using a number of additives, such as chloride, SPS as accelerator, PEG as inhibiter and quaternary diallylamine as leveler, we enabled that the electrodeposition time have been shortened from 60 min to 35 min.…”

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confidence: 99%

Via Filling Electrodeposotion of 4μm Diameter Via by Periodical Reverse Current

et al. 2013

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To enable low power consumption and the access speed increase, three dimensional packaging of semiconductor chips has been proposed. In particular, a high-aspect ratio through silicon via(TSV) allows short chip to chip interconnection. 4 μm diameter and aspect ratio of 7.5 via TSV has filled. The perfect via filling was achieved within 25 minutes with the increasing i rev /|i on | ratios of periodic reverse pulse current waveform. In addition, we evaluated produced cuprous ion concentration during electrodeposition by using rotating ring disk electrode(RRDE). From the electrochemical measurement by RRDE, cuprous ion concentration on the reactive surface was markedly increasing with the increasing i rev /|i on | ratios. At i rev /|i on | ratio of large(i rev /|i on | = 6.0), a large amount of cuprous ion concentration produces during copper dissolution by reverse current and cuprous ion remain at the via bottom. High cuprous ion concentration at the via bottom accelerate deposition at the via bottom and achieve bottom up filling.

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“…[6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.…”

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confidence: 99%

“…[1][2][3][4][5] Recently, through-silicon vias (TSVs) have also been metallized by copper electroplating for the interconnection of threedimensional (3D) IC chip stacking packaging. [6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.…”

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confidence: 99%

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

Lin

Huang

Wang

et al. 2015

ECS Electrochemistry Letters

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A nickel-tungsten alloy plating formula was developed to electrochemically fill the microvias of printed circuit boards and the through-silicon vias (TSVs) of wafers. The plating solution was composed of Ni(SO 3 NH 2 ) 2 , citric acid, sodium citrate, Na 2 WO 4 , chloride ions, and 2-mercapto-5-benzimidazolesulfonic acid. A void-free Ni-W superfilling of a microvia and a TSV were achieved. The tungsten content in the filled alloy varied from 1.5 atom% to 5.5 atom%, depending on the plating temperature. The coefficient of thermal expansion of the filled Ni-W was theoretically calculated according the tungsten content, which was lower than that of copper. Microvia filling by copper electroplating has been widely employed to fabricate state-of-the-art printed circuit boards (PCBs) for interconnection, especially for integrated circuit (IC) packaging substrates.1-5 Recently, through-silicon vias (TSVs) have also been metallized by copper electroplating for the interconnection of threedimensional (3D) IC chip stacking packaging. [6][7][8][9][10][11][12][13] Copper is a good conductor but its coefficient of thermal expansion (CTE) is high. Therefore, issues related to CTE mismatch between the conducting materials and the dielectric materials arise in PCB and 3D packaging with high-density interconnections.Numerous authors have reported that the high CTE of the copper filled in the TSVs results in stress impacts on silicon substrates. [14][15][16][17] Copper atoms diffuse from the TSV due to thermal cycling, leading to void formation in the TSV. 18,19 The copper protrusion on the TSV caused respectively by thermal expansion and diffusion of copper lattices and atoms may destroy stacked IC chips. [20][21][22] Copper must be replaced by tungsten 23 or nickel 24,25 to overcome the issue of CTE mismatch.Although the CTE of tungsten is very low, 14,26 it cannot be electrochemically plated in an aqueous electrolyte. Fortunately, tungsten can be induced to co-deposit with nickel. [27][28][29][30][31][32] In this work, a Ni-W alloy plating formula that can achieve Ni-W bottom-up filling of microvia was developed. This plating formula can fill the microvia of PCBs and can also fill TSVs. The Ni-W filled TSVs exhibit good thermal stability after being annealed at 500• C for 4 h. ExperimentalThe dimensions of the PCB fragments cut for the Ni-W filling plating were 4.2 × 6.0 cm 2 . The microvias were formed by CO 2 laser ablation. The diameter and depth of the microvias were 80 μm and 40 μm, respectively. The sidewalls of the microvias were metallized by electroless copper plating in advance to deposit a 2-3 μm thick layer of copper before the filling plating.TSVs were formed by a deep reactive ion etching (DRIE) process (i.e., the Bosch process). The thickness of the isolation layer (i.e., SiO 2 ) in the TSVs formed by thermal oxidation was approximately 1-3 × 10 3 Å. The barrier layer was a TiN film with a thickness of 500 Å, which was conformably deposited by atomic layer deposition (ALD) for 600 cycles. The seed layer was depo...

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High Speed Through Silicon Via Filling by Copper Electrodeposition

Cited by 61 publications

References 4 publications

Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor

Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor

Via Filling Electrodeposotion of 4μm Diameter Via by Periodical Reverse Current

Microvia Filling with Nickel-Tungsten Alloy to Decrease the Coefficient of Thermal Expansion of Electronic Circuit Interconnections

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