Geometrical analysis of product layout as a powerful tool for DFM (Invited Paper)

Roessler, Thomas; Thiele, Joerg

doi:10.1117/12.595062

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…TF-MEEF = max(|EDGE wafer@(m+Δ /m-Δ ,defocus) -EDGE wafer@(m,best focus) | )/Δ (3) There may arise a question that whether the TF-MEEF instead of the PW-MEEF (through Process Window MEEF) will be enough for the purpose of layout verification. The TF-MEEF, in a sense, can surely be used as a metric for the design verification without losing the robustness of the verification because the MEEF is closely related with the NILS, which can be directly translated into exposure latitude in some specific cases.…”

Section: Tf(through Focus)-meef and Mask Uniformitymentioning

confidence: 99%

“…Lithographer's understanding of DFM can be interpreted as 'a process worthy design' and the requirements derived from this understanding needs to be well defined and delivered to the designer as a necessary condition for the final yield promising design. There are two approaches in manipulating the designer's layout: one is a feed-forward method to restrict design space based on lithography rules [1,2,3] and the other is a feed-back method which is using a robust metric devised by the lithographer to alarm the designer during the routing [4].…”

Section: Introductionmentioning

confidence: 99%

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Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

et al. 2006

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Design for Manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designer's intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographer's understanding of DFM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy.In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), Through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. The DFM can be viewed as flattening the TF-MEEF across the design.

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Section: Tf(through Focus)-meef and Mask Uniformitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

et al. 2006

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“…The lithography simulation tool is also used for applications such as model-based design rule checks [3][4][5][6][7] and process window analysis, [8][9][10] as well as timing analysis based on simulated critical dimensions. 11 Other than these applications, there could be different applications of the lithography simulation tool such as design for manufacturability ͑DFM͒ rule development and transistor effective parameter back-annotation, as developed and described in this work.…”

Section: Introductionmentioning

confidence: 99%

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Wang

et al. 2007

J. Micro/Nanolith. MEMS MOEMS

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We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction ͑pre-OPC͒ layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability ͑DFM͒ compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products ͑designed with 90-nm design rules͒ are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope ͑SEM͒ images validate the approach. © 2007 Society of Photo-Optical Instrumentation Engineers.

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Modeling edge placement error distribution in standard cell library

et al. 2006

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In this work we present a predictive model for the edge placement error (EPE) distribution of devices in standard library cells based on lithography simulations of selective test patterns. Poly-silicon linewidth variation in the sub-100nm technology nodes is a major source of transistor performance variation (e.g., Ion and Ioff) and circuit parametric yield. It has been reported that significant part of the observed variation is systematically impacted by the neighboring layout pattern within optical proximity. Design optimization should account for this variation in order to maximize the performance and manufacturability of chip designs.We focus our analysis on standard library cells. In the past the EPE characterization was done on simple line array structures. However, the real circuit contexts are much more complex. Standard library cells offer a nice balance of usability by the designers and modeling complexity. We first construct a set of canonical test structures to perform lithography simulations using various OPC parameters and under various focus and exposure conditions. We then analyze the simulated printed image and capture the layout-dependent characteristics of the EPE distribution. Subsequently, our model estimates the EPE distribution of library cells based on their layout. In contrast to a straight-forward simulation of the library cells themselves, this approach is computationally less expensive. In addition the model can be used to predict the EPE distribution of any library cells and not limited to those that are simulated. Also, since the model encapsulates the details of lithography, it is easier for designers to integrate into design flow.

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Geometrical analysis of product layout as a powerful tool for DFM (Invited Paper)

Cited by 3 publications

References 9 publications

Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Modeling edge placement error distribution in standard cell library

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