Modeling edge placement error distribution in standard cell library

Abstract

In this work we present a predictive model for the edge placement error (EPE) distribution of devices in standard library cells based on lithography simulations of selective test patterns. Poly-silicon linewidth variation in the sub-100nm technology nodes is a major source of transistor performance variation (e.g., Ion and Ioff) and circuit parametric yield. It has been reported that significant part of the observed variation is systematically impacted by the neighboring layout pattern within optical proximity. Design optimization should account for this variation in order to maximize the performance and manufacturability of chip designs.We focus our analysis on standard library cells. In the past the EPE characterization was done on simple line array structures. However, the real circuit contexts are much more complex. Standard library cells offer a nice balance of usability by the designers and modeling complexity. We first construct a set of canonical test structures to perform lithography simulations using various OPC parameters and under various focus and exposure conditions. We then analyze the simulated printed image and capture the layout-dependent characteristics of the EPE distribution. Subsequently, our model estimates the EPE distribution of library cells based on their layout. In contrast to a straight-forward simulation of the library cells themselves, this approach is computationally less expensive. In addition the model can be used to predict the EPE distribution of any library cells and not limited to those that are simulated. Also, since the model encapsulates the details of lithography, it is easier for designers to integrate into design flow.

Key directions and a roadmap for electrical design for manufacturability

“…Standard techniques -DOEs, simulation structures, and silicon TEGs -must afford rigorous foundations for model-based and statistical design. Prototypes might include [3] (CMP fill/extraction) and [9] (post-OPC litho contour prediction).…”

Mechanism of Precursor Blocking by Acetylacetone Inhibitor Molecules during Area-Selective Atomic Layer Deposition of SiO2

“…The fabrication of these layers currently relies on repeated deposition, photolithography, and etching steps . However, photolithography-based fabrication schemes typically result in edge placement errors (EPEs), which are discrepancies between the intended and actual feature positions. − For sub-5 nm technology nodes, these EPEs become the bottleneck in the fabrication of reliable devices. ,, As a result, several self-aligned and bottom-up fabrication schemes are being explored, either to complement or replace steps of the traditional top-down fabrication schemes. The starting point for self-aligned fabrication by area-selective deposition (ASD) is a predefined pattern consisting of a set of materials on which deposition is desired (i.e., the growth areas) and a set of materials on which deposition should be avoided (i.e., the non-growth areas).…”