Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Abstract

We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction ͑pre-OPC͒ layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability ͑DFM͒ compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products ͑designed with 90-nm design rules͒ are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope ͑SEM͒ images validate the approach. © 2007 Society of Photo-Optical Instrumentation Engineers.

<title>Design-of-experiments based design rule optimization</title>

“…Since only neighboring layers interact, we can construct separate binary factorial experiments for each set of interacting rules. Then the reduction achieved by splitting a single large factorial experiment to multiple smaller factorial experiments is as shown in Equation 7.…”

“…al. 10 7 on the other hand, performed full chip lithography simulation to first find hot-spots which are then used to improve the design rule set. Lithography simulation based approaches cited above do not evaluate the design impact of DR values, either with respect to their impact on chip area or any electrical metric like performance, power and signal integrity.…”