Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k 1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [4,5] , it has been shown that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask.The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.
It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask.Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.
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