For advanced technology nodes, a large amount of effort must be spent to optimize area critical full-custom layouts with respect to their manufacturability. Due to the strong irregularity and two-dimensionality of these layouts, it appears impossible to fully capture the corresponding complex requirements with design rules in order to be able to perform a rule-based physical verification in form of a "design rule check" (DRC). Alternative approaches have to be found and one of them is presented in this paper. The complexity of the DRC can be significantly reduced for rules focused on process aspects. Those rules can be replaced by a "simulation rule check" (SRC), where at first process simulations (like e.g. lithography) are done and then a set of straightforward rules is applied to geometrical entities representing the simulation output instead of the layout geometry. Thus, this new set of rules works more directly on the core of the matter. The "litho-friendly design environment" (LFD) provided by Mentor Graphics offers the tools for this approach. The SRC includes intra-layer checks like area, width, and space checks as well as interlayer checks, such as overlap. To the physical designer, SRC violations are presented in a DRC like fashion, including error scoring and classification. This paper will demonstrate the application of LFD and highlight the usability of this infrastructure for layout optimization using an SRC for physical verification.
Recently, "design for manufacturability" (DFM) has become a veritable buzzword in the semiconductor manufacturing community. DFM activities cover a broad spectrum ranging from the improvement of the electrical and structural robustness against process variations to the reduction of layout parts critical for statistically distributed defects or sensitive to systematic process weaknesses. In our work we focus only on those aspects of DFM concerned with the structural integrity of patterns on the wafer. We show that a purely geometrical analysis of product layouts offers a powerful tool to strengthen the link between design and manufacturing. It allows, for instance, a visualisation of the extent to which intra-and inter-layer design rules determine the geometry configurations dominating the layout and the identification of patterns occurring only rarely. Furthermore, in combination with the geometry-resolved information about the accuracy of "optical proximity correction" (OPC) models and "critical dimension" (CD) control, such an analysis provides valuable input for systematic improvements on both, the product layout and manufacturing process side. In this sense it supports the progress towards making real designs still manufacturable at the limits of process tool capabilities.
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