Beyond rule-based physical verification

Hoppe, W; Roessler, Thomas; Torres, J. Andres

doi:10.1117/12.686604

Cited by 11 publications

(6 citation statements)

References 7 publications

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“…One way for viewing the effect of the exposure and focus process window is to highlight a band representing the variation in simulated CDs across all the models. 4 Fig. 4 shows a process band around a gate CD violation.…”

Section: Nomentioning

confidence: 98%

Intelligent visualization of lithography violations

Ziger

2007

SPIE Proceedings

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Section: Nomentioning

confidence: 98%

Intelligent visualization of lithography violations

Ziger

2007

SPIE Proceedings

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“…The contours for each process variation combination may be overlaid to determine the range of feature edge locations that can be expected in manufacturing. 3,4 These overlaid contours are often referred to as process variability bands, or PV bands ( Figure 2). …”

Section: Printability Verification Flowmentioning

confidence: 99%

Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification

Cain

Capodieci

2009

SPIE Proceedings

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In this work, we present a novel application of layout printability verification (LPV) to assess the scalability of physical layout components from 32 nm to 28 and 22 nm with respect to process variability metrics. Starting from the description of a mature LPV flow, the paper illustrates the core methodology for deriving a metric for design scalability. The functional dependency between the scalability metric and the scaling factor can then be modeled to study the scaling robustness of a set of representative layouts. Conversely, quantitative data on scalability limits can be used to determine which design rules can be pushed and which must be relaxed in the transition from 32 to 22 nm.

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“…Manufacturability concerns are addressed at each stage of the design cycle (at library level, core and integration levels) through application of iterative design improvement using modelbased patterning simulation [2]. The application of simulation tools during the design cycle allows the manufacturing team to identify layout patterns that are of high value to design, but have limited patterning process window.…”

Section: Design Versus Manufacturing Considerationmentioning

confidence: 99%

Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

et al. 2011

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For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of modelbased simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield.The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.The time when design rule (DR) correct layouts could be processed in the manufacturing lines with no or minimal post tape out intervention is long past. Many advanced techniques have been developed to improve the lithographic entitlement. Their success allowed for the design to concentrate on producing best manufacturable "target" design in the hope that the manufacturing can reproduce it on wafer, but things became more complicated as the critical dimension shrank further. To control the risk of systematic failure the tendency is to make the design rules more complex, but this in itself does not guarantee pattern fidelity. With fewer companies manufacturing integrated circuitry and with increasing technology complexity, designers have become more interested in using all the information available to improve design manufacturability. This and the well understood increased difficulty of capturing design intent leads to increased motivation for manufacturing, technology development, and design teams to collaborate to create high yield parts creating a "must fix" contract. Design and process co-optimization becomes the norm. This process encompasses the tool and tuning capability to determine critical constructs, identifying those with the worst performance, and the guidance to resolve those manufacturability issues. A margin for adverse variation is also accounted for within the performance consideration.The goal of this paper is to show that a consistent framework provides a mechanism to detect and rank manufacturability problems in design, while guiding the correction process. A predefined set of guidelines is needed to understand what degree of process knowledge is sufficient for building a useful DfM tool.

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Beyond rule-based physical verification

Cited by 11 publications

References 7 publications

Intelligent visualization of lithography violations

Intelligent visualization of lithography violations

Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification

Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

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