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Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBM's early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

The International Technology Roadmap for Semiconductors lists F2 (λ =157nm) optical lithography and extreme ultraviolet next generation lithography as the two most feasible lithography solutions for the 70nm technology node. It is likely that both of these solutions will be late, forcing ArF (λ =193nm) lithography to operate at unprecedented resolution levels. Theoretically, alternating phase shifted masks ("altPSM") can achieve the resolution required to manufacture 70nm logic products with ArF lithography equipment, but technical and logistical challenges associated with the broad implementation of altPSM require novel and invasive EDA solutions which have caused the industry to shy away from altPSM in the past. One of the biggest such challenges is the creation of robust design rule checking (DRC) tools which can predict whether a given layout has a valid, manufacturable altPSM solution. This paper takes a detailed look at the technical and practical issues associated with altPSM design rules and DRC.

ABSTRA CTWhile the hcneftts of alternating phase shifted masks in improving lithographic lOce windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufticturing and Development facility to understand the technical and logistical issues associated with the apphcation of alternating phase shifted mask technology to the gate level of a lull microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted niask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design. added required phase regions. and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based (lie to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks presents a design and data preparation overhead, hut the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

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