Gate Stack Architecture Analysis and Channel Engineering in Deep Sub-Micron MOSFETs

Abstract

Scaling of metal-oxide-semiconductor (MOS) transistors to smaller dimensions has been a key driving force in the IC industry. As we approach the sub-quarter micron regime, a whole new set of problems regarding the device performance arises. One of the major concerns is the high gate leakage current. To address this problem, a lot of effort has been concentrated on the use of the so-called "high-K dielectrics" as gate insulators. However, the implications of using these materials on the electrical performance of MOS devices need to be studied. This work is an effort towards the same. There has also been a lot of discussion about the trade-offs related to the use of retrograde channel profiles in deep sub-micron transistors. It is also shown in this work that a retrograde profile can be optimized to have an advantage over uniform doping.

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

“…The high -k gate stack also improve SCEs like (drain induced barrier lowering (DIBL) and hot carrier effects (HCEs), channel length modulation (CLM)) and increase drive current to leakage current ratio (I on /I off ) in sub-100 nm regime as reported in various studies [22][23][24].…”

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

“…a thick layer of high-k oxide is sandwiched over a thin layer of SiO 2 ) has been proposed by Hu and Wong [14,15]. The high-k gate stack also improves SCEs like drain induced barrier lowering (DIBL), hot carrier effects (HCEs), channel length modulation (CLM) and increases the drive current to leakage current ratio (I on /I off )i ns u b -1 00n m DG-MOSFETs as reported in various studies [16,17],.I na recent work [18], a detailed investigation on the role of highk gate dielectric on various parameters by considering both single layer and gate stack configurations has been presented with the aim to optimize the high-k gate dielectric. Similarly, t h eD Mg a t ed e v i c e s ,i nw h i c ht w od i f f e r e n tw o r kf u n ctions are used to form the gate, show promising results in the reduction of SCEs [19,22].…”

Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET

“…The high K and Si system results in unacceptable level of bulk fixed charge, high interface trap density and low silicon interface carrier mobility [17]. Consequently, extremely thin layer of interfacial oxide is used as a coating to reduce the interface trap density thus increasing the device performance [18]. The gate stack architecture (GSA) was proposed in order to reduce the gate leakage and leads to an enhancement of average electric field in the channel, thereby improving carrier transport efficiency [19,20].…”