Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET

Abstract

Abstract-A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.Index Terms-Dual metal gate stack architecture (DMGSA), surrounded/cylindrical gate MOSFET (CGT/SGT), short channel effects (SCEs)

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

“…Therefore, to lower down SCE's, engineering of placing the dielectric material is required. A high K dielectric concept has been implemented in conventional cylindrical surrounded MOS by the authors in [51,53]. The material having a low dielectric constant can be placed at the drain end whereas high dielectric material is placed at the source end.…”

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

“…However it is achieved at the cost of current drivability and gain. In order to improve the device operation characteristics, high-k dielectric [22,23] has been widely incorporated as a gate stack. Ghosh et al [23] showed that gate stack architecture with a high-k dielectric on a dual metal CSG MOSFET device decreases the minimum surface potential of the device, which consequently increases the carrier transport efficiency and prevents the direct tunneling leakage current.…”

“…In order to improve the device operation characteristics, high-k dielectric [22,23] has been widely incorporated as a gate stack. Ghosh et al [23] showed that gate stack architecture with a high-k dielectric on a dual metal CSG MOSFET device decreases the minimum surface potential of the device, which consequently increases the carrier transport efficiency and prevents the direct tunneling leakage current. Although the use of asymmetric gate stack [24,25] has been studied in the past, the same has not been incorporated on a JL MOSFET.…”

Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

“…Gate material engineering (GME) is one of them proposed by Chiang et al [12] and Kumar et al [13]. In GME technique, gate metal work function is tuned so that the metal with high work function accelerates charge carriers near the source region while the low work function metal is chosen at drain region [14], [15]. These expedited charge carriers collected at drain region provide higher ION.…”