Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

Sharma, Aniruddh; Jain, Arushi; Pratap, Yogesh; Gupta, R. S.

doi:10.1016/j.sse.2016.05.016

Cited by 37 publications

(14 citation statements)

References 26 publications

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“…To improve the performance in DG-JLFET for the parameters such as off current, on current, transconductance, DIBL and threshold voltage, many gate and channel engineering approaches are adopted [7][8][9][10]. The gate dielectric materials are required mainly for having good insulating properties and high capacitance value [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Kumar

Vashishath

Gupta

et al. 2022

Silicon

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This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson's equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

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Section: Introductionmentioning

confidence: 99%

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Kumar

Vashishath

Gupta

et al. 2022

Silicon

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“…It became possible due to the inclusion of this dielectric just beneath the gate electrode. Although, the use of both dielectrics (Al 2 O 3 , HfO 2 ) has been studied in the past for RF and reliability performance of vacuum JLFET [14], [15]. But the comparative investigation of CP based high-κ/vacuum dielectric DL-JLFET (VacuHDL-JLFET) with conventional DL and JLFETs has not been performed yet.…”

Section: Introductionmentioning

confidence: 99%

Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric

Kumar

Panchore

Bramhane

et al. 2021

Silicon

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A comparative evaluation of channel hot carrier (CHC) reliability and pursuance of dopingless FET (DL JLFET) and junctionless FET (JLFET) are studied for various dielectrics and compared with conventional dielectric (SiO 2 ) JLFET. The use of dielectrics such as vacuum near the drain and the high-κ (HfO 2 ) near the source in DL JLFET (VacuHDL JLFET) allows better pursuance and reliability against channel hot carrier (CHC) effects. A simulation study has shown that the pursuance of VacuHDL in terms of I on /I off ratio is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL, HJL and JL. Similarly, the intrinsic delay of VacuHDL is improved by 9.5%, 56.8 % and 58.7 %, respectively, in comparison with VacuDL, VacuHJL and VacuJL. Hence, VacuHDL is a potential candidate for digital circuit applications. Further, we have found that vacuum-based HDL and HJL are more immunes against CHC stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9 % and 17.5 %, respectively, in comparison with conventional dialectic (SiO 2 ) based DL and JL which is 10.4 % and 20.5 %. Hence, the incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric.

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“…According to Yu et al [12], a good enhancement in transfer and output characteristics is achieved in their experimental study of strained SiGe quantum well p-MOSFETs with higher-k dielectric. Evenly, Sharma et al [13] have shown that the use of high k materials in JL-CSG MOSFET device contributes to the improvement of the electrical and thermal characteristics.…”

Section: Introductionmentioning

confidence: 99%

Numerical simulation of Gate shape effect on Self-Heating in nano-MOSFET Transistors with high-k dielectric

Belkheria¹,

Echouchene²,

Bajahzar³

et al. 2021

Preprint

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The aim of the present work is to investigate numerically the self-heating effect (SHE) in MOSFET transistors based on high-k material taking into account the deformation of the gate under the SHE. The SHE inside the MOSFET transistor is calculated using the electrothermal model based on heat transfer equation coupled with semiconductor equations. The electrothermal model have been solved in 2D-dimension using the finite element method. The high-k dielectric HfO2 have been used as gate oxide. Several gate shapes have been used to analyze their impact on SHE. It is observed that the reduction of equivalent oxide thickness (EOT) reduces the SHE in the MOSFET transistor based in high-k dielectric material. the temperature peak increases quadratically with drain voltage for all MOSFET structures. A decrease in self-heating effect is achieved using the square gate shape.

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Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

Cited by 37 publications

References 26 publications

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric

Numerical simulation of Gate shape effect on Self-Heating in nano-MOSFET Transistors with high-k dielectric

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