Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric

Abstract

A comparative evaluation of channel hot carrier (CHC) reliability and pursuance of dopingless FET (DL JLFET) and junctionless FET (JLFET) are studied for various dielectrics and compared with conventional dielectric (SiO 2 ) JLFET. The use of dielectrics such as vacuum near the drain and the high-κ (HfO 2 ) near the source in DL JLFET (VacuHDL JLFET) allows better pursuance and reliability against channel hot carrier (CHC) effects. A simulation study has shown that the pursuance of VacuHDL in terms of I on /I off ratio is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL, HJL and JL. Similarly, the intrinsic delay of VacuHDL is improved by 9.5%, 56.8 % and 58.7 %, respectively, in comparison with VacuDL, VacuHJL and VacuJL. Hence, VacuHDL is a potential candidate for digital circuit applications. Further, we have found that vacuum-based HDL and HJL are more immunes against CHC stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9 % and 17.5 %, respectively, in comparison with conventional dialectic (SiO 2 ) based DL and JL which is 10.4 % and 20.5 %. Hence, the incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric.

Assessment of BTI‐induced deterioration in vacuum based undoped structure

“…Also, the electric filed in dopingless structure is quite less than conventional junctionless structure, thus making it more reliable from aging effect due to CHC. [5][6][7][8][9] However, the reliability of these scaled-up devices has become extremely important and it depends on other stress factors also, for example, bias temperature instability (BTI). BTI in short channel transistor occurs due to reduced thickness gate oxide which leads to increase the electric field in the oxide and thus deteriorates electrical performance of the device.…”

“…In DLJLFET structure, the silicon region doping is almost intrinsic; therefore, it is less susceptible to RDF and exhibits higher ON‐state current and smaller leakage current. Also, the electric filed in dopingless structure is quite less than conventional junctionless structure, thus making it more reliable from aging effect due to CHC 5–9 . However, the reliability of these scaled‐up devices has become extremely important and it depends on other stress factors also, for example, bias temperature instability (BTI).…”

“…Many reports have been published on high‐k and vacuum‐based gate dielectrics for the junctionless cylindrical surrounding gate (JL‐CSG) MOSFET, 16 junctionless nanowire transistor (JNT), 17 gate all around MOSFET 18 . In our previous work, 9 we have used an asymmetric combination of high‐k $$$ \left({\mathrm{HfO}}_2\right) $$$ at the source side and vacuum at the drain side, which improves current transport efficiency and reduces the effect of hot carrier by reducing the electric field near the drain side. However, to the best of our knowledge, no study has been done for assessment of BTI stress in $$$ \mathrm{high}-\kappa /\mathrm{vacuum} $$$ based dual gate dopingless JLFET (HKV‐DLJLFET).…”