Assessment of BTI‐induced deterioration in vacuum based undoped structure

Abstract

In this paper, an assessment of bias temperature instability (BTI) in based dual gate dopingless JLFET (HKV‐DLJLFET) is carried out at 15 nm technology node. For this, the gate dielectric of HKV‐DGDLJLFET is made of asymmetric combination of and vacuum dielectrics near the source/drain (S/D) side, which significantly minimizes the leakage current and enhances the reliability. Our simulation study have shown that the n‐type HKV‐DGDLJLFET exhibits 2.28 and 2.45 times less deterioration in drain current and transconductance respectively, than n‐type HKV‐DGJLFET due to positive BTI (PBTI) for 2000 seconds at . Further, we have found that n‐type HKV‐DGDLJLFET has less deterioration in and due to BTI stress for different time spans. Hence, adding vacuum dielectric to the drain side lowers the BTI stress at high temperatures and makes it last longer.